Ex Parte Reents et al

Board of Patent Appeals and Interferences

May 22, 2007

09257521 (B.P.A.I. May. 22, 2007)

The opinion in support of the decision being entered today was not written for
publication and is not binding precedent of the board
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UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_____________

Ex parte DANIEL B. REENTS, DONALD G. CRAYCRAFT, 12
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and CARL K. WAKELAND
_____________

Appeal 2007-0219
Application 09/257,5211
Technology Center 2100
______________

Decided: May 22, 2007
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Before JOHN C. MARTIN, JOSEPH F. RUGGIERO, and
JOSEPH L. DIXON, Administrative Patent Judges.
MARTIN, Administrative Patent Judge.

DECISION ON APPEAL
This is an appeal from the Examiner’s rejection of Claims 30-64, all of the
pending claims, under 35 U.S.C. § 103(a).2

1 Filed February 25, 1999.
2 The Examiner has withdrawn the rejection of Claims 34, 41, and 45 under
the first paragraph of 35 U.S.C. § 112. Answer 18-19.
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We have jurisdiction under 35 U.S.C. § 134(a).
A. APPELLANTS’ INVENTION
The subject matter of the invention is succinctly described in the title of the
application: “A Communication Protocol Processor Having Multiple
Microprocessor Cores Connected in Series and Dynamically Reprogrammed
During Operation Via Instructions Transmitted Along the Same Data Paths Used to
Convey Communication Data.”
The communication protocol processor 32 (Fig. 3) includes a bus port 36, a
communication network port 38, a transmit unit 40, and a receive unit 42. As
shown in Figure 4, transmit unit 40 includes serially connected plural
microprocessor cores 48 each having an associated code memory unit 50 and data
memory unit 52. As shown in Figure 6, each code memory unit 50 includes a basic
operating code portion and a protocol processing code portion. Each
microprocessor core performs one or more tasks required to encapsulate the serial
transmit data stream into frames in accordance with the selected communication
protocol. Specification at 15, ll. 1-3. For example, the first, second, third, and
fourth microprocessor cores may respectively perform the following tasks: a CRC
generation function; a zero-bit insertion function; a flag and abort frame processing
function; and an output function. Id. at 16 (as amended Nov. 21, 2002).
Appellants’ invention permits the contents of the protocol processing code
portion of a code memory unit 50 to be modified during operation of the
communication protocol processor 32 to reflect a change or modification of the
communication protocol. Id. at 6, ll. 11-13. In this regard, Figure 7 shows a code
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packet 60 for conveying instructions and data to a microprocessor core. Id. at 18,
ll. 7-8. The code packet includes an address field 64 identifying the
microprocessor core (and more particularly its associated code memory unit 50) to
which the packet is directed. Id. at 18, ll. 15-18. Each microprocessor core
includes circuitry to recognize the occurrence of such a code packet and to
determine whether it is the intended recipient of the code packet. Id. at 18, ll. 20-
21. If a microprocessor core detects a code packet having a unique identifier
assigned to that microprocessor core, the microprocessor core writes the
instructions and data contained within the code packet into the protocol processing
portion of the corresponding code memory unit 50 and does not forward that code
packet to the next microprocessor core along the data path. Id. at 18, ll. 22-29.
B. GROUPING OF THE CLAIMS
The independent claims on appeal are Claims 30, 41, 52, 57, and 61.
Appellants separately argue these claims and many of their dependent claims.
C. THE REFERENCES AND REJECTIONS
The rejections are based on the following references:
Nair US 5,724,356 Mar. 3, 1998
Bennett US 6,122,670 Sep. 19, 2000
(filed Oct. 30, 1997)
Oliver US 6,292,484 B1 Sep. 18, 2001
(filed June 10, 1998)

Brown US 6,397,287 B1 May 28, 2002
(filed Jan. 27, 1999)
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Wright US 6,442,669 B2 Aug. 27, 2002
(filed June 29, 19983)
The claims stand rejected under 35 U.S.C. § 103(a) for obviousness over the
following combinations of references:4
(1) Claims 30, 31, 33-37, and 57-59 -- Wright in view of Nair;
(2) Claims 32 and 60 -- Wright in view of Nair and further in view of
Bennett;
(3) Claims 38-40 -- Wright in view of Nair and further in view of Brown;
(4) Claims 41-48 -- Nair in view of Oliver and further in view of Wright;
(5) Claims 46-48 -- Nair in view of Oliver, further in view of Wright, and
further in view of Bennett; and
(6) Claims 49-64 – Nair in view of Oliver, further in view of Wright, and
further in view of Brown.
D. PRINCIPLES OF LAW
“[T]he examiner bears the initial burden, on review of the prior art or on any
other ground, of presenting a prima facie case of unpatentability.” In re Oetiker,
977 F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed. Cir. 1992). A rejection under
35 U.S.C. § 103(a) must be based on the factual determinations required by the,
namely, (1) the scope and content of the prior art, (2) the level of ordinary skill in
the art, (3) the differences between the claimed invention and the prior art, and

3 Specifically, filed November 30, 2000, as a continuation of 09/106,436,
filed June 29, 1998 (Patent 6,195,739).
4 Based on Appellants’ summary of the grounds of rejection (Br. 9), which
the Examiner has indicated is correct. Answer 2, para. (6).
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(4) objective indicia of non-obviousness. DyStar Textilfarben GmbH & Co.
Deutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1360, 80 USPQ2d 1641,
1645 (Fed. Cir. 2006) (citing Graham v. John Deere Co., 383 U.S. 1, 17, 148
USPQ 459, 467 (1966)). In addition, “there must be some articulated reasoning
with some rational underpinning to support the legal conclusion of obviousness.”
KSR Int’l v. Teleflex, Inc., 127 S. Ct. 1727, 1741, 82 USPQ2d 1385, 1396 (2007)
(quoting In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006)).
Such reasoning can be based on interrelated teachings of multiple patents, the
effects of demands known to the design community or present in the marketplace,
and the background knowledge possessed by a person having ordinary skill in the
art. KSR, 127 S. Ct. at 1731, 82 USPQ2d at 1396.
E. THE REJECTION OF CLAIMS 30, 31, 33-37, AND 57-59
OVER WRIGHT IN VIEW OF NAIR
Of the claims rejected over Wright in view of Nair, only Claims 30 and 57
are independent. Claim 57, the broader claim, reads:
57. A method, comprising:
receiving a serial data stream from an interface port;
performing a protocol processing operation on said serial
data stream; and
configuring at least part of said protocol processing
operation by embedding code packets within said data stream.
Claim 30 similarly calls for using embedded code packets to configure a protocol
processing operation that is being performed on the serial data stream and adds
other limitations, as does independent Claim 52.
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The Examiner cites Nair as evidence that it was known to use an embedded
code packet in a serial data stream to configure at least part of a protocol
processing operation being performed on the serial data stream. Nair discloses an
intelligent local area network (LAN) modem node 100 (Fig. 1) which allows PCs
30 on LAN 20 to communicate with off-LAN devices 40, 50, 60, 70, 80 (also
called “remote resources”) and which allows off-LAN (remote) PCs access to
network resources without tying up other PCs 30 on the LAN ("network PCs").
Nair, col. 3, ll. 43-59.
Communication between the network PCs 30 and LAN modem node 100 is
made possible through use of a special packet protocol for transferring data and
control information between the network PCs 30 and the LAN modem node 100.
Id. at col. 4, ll. 42-65. This special packet protocol is embedded within the IPX
packet protocol that is used for communicating over the LAN 20. Id. The IPX
protocol transfers the special packets as raw serial data without any knowledge of
the content of those packets. Id. The packets of the node are decoded by the
software running at the LAN modem node and at the network PCs recipient site.
Id. The software which handles this function in the LAN modem node is called the
“async server.” Id.
We agree with the Examiner’s conclusion that the recited “serial data
stream” reads on Nair’s stream of IPX packets and that the recited “code packets
embedded within said data stream” read on the special packets embedded therein.
Answer at 6 (citing Nair, col. 4, ll. 37-58). Appellants’ argument that “the cited
portions of Nair merely disclose the embedding of data formatted according to a
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‘special packet protocol . . . within the IPX packet protocol which is used for
communicating over the LAN 20’ (col. 4, lines 46-50),” Br. 13, and that “neither
Nair nor Wright teach or suggest any aspect of embedding code packets within a
serial data stream,” Br. 21, is not persuasive. The term “code packet” is not
defined in Appellants’ Specification and therefore must be given its broadest
reasonable interpretation. In re Morris, 127 F.3d 1048, 1054, 44 USPQ2d 1023,
1027 (Fed. Cir. 1997). Nair’s special packets can properly be characterized as
“code packets” because they are “decoded” by the software running at the LAN
modem node and the network PCs (col. 4, ll. 52-54).
Various types of special packets and their corresponding protocols are
discussed in Nair at columns 10-17 and depicted in Figures 15A-15J. Nair, col. 10,
ll. 8-14. The Examiner held (Answer 20) that the recited step of using embedding
code packets within the data stream to configure at least part of said protocol
processing operation that is being performed on the serial data stream reads on the
functions performed by any of the following four types of special packets:
(1) The “connect response packet” (col. 14, l. 9) of Figure 15C, which
“shows the communication protocol for when a network PC requests a connection
to the async server” (col. 11, ll. 62-63).
(2) The “flow control packet” (col. 15, ll. 9) of Figure 15D, which “shows
the communication protocol for sending data from a network PC to the async
server to be sent out to a designated resource” (col. 14, ll. 44-46).
(3) The “change parameters packet” (col. 15, l. 64) of Figure 15F, which
“shows the communication protocol which allows a network PC to change the
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operating parameters of the resource” (col. 15, ll. 50-52), such as the baud rate of
the resource. See column 15, lines 52-54 (“[I]f at any time the network PC needs
to change the baud rate at which it communicates with a resource, it can do so by
sending a CHANGE PARAMETERS packet.”).
(4) The “control packet” (col. 16, l. 24) of Figure 15H, which “shows the
communication protocol through which either a network PC or the async server
may set or get the status of certain control signals from each other” (col. 16, ll. 19-
23).
It is apparent from the Examiner’s specific holding that “information that
changes bandwidth or the type of signal or new operation parameter of a connected
resource will change how a protocol process operation works” (Answer 21) that he
is primarily relying on the “change parameters packet” and the “control packet.”
We do agree that either of these special packets is used to configure (i.e., set or
change) a protocol processing operation that is being performed on the serial data
stream, as required by independent Claims 30 and 57. The effect of using the
“change parameter packet” is to alter the operation of a resource (e.g., its baud
rate). Even assuming this alteration can properly be characterized as an alteration
of the protocol of the resource, it does not amount to configuring a protocol
operation that is being performed on the serial data stream, as required by the
claims. Likewise, using a “control packet” to set the status of a control signal does
not configure a protocol operation that is being performed on the serial data stream.
Nor is such a configuration step achieved by use of the “connect response packet”
or the “flow control packet.” We therefore agree with Appellants that while the
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special packets in the serial data stream are processed in accordance with protocol
operations set forth in the Figures 15A-15J, those protocol operations are not set or
altered in response to the special packets. Reply Br. 3.
The above-noted deficiency in Nair is not remedied by the subject matter
relied on in Wright by the Examiner. The Examiner cited Wright as evidence of
the obviousness of modifying Nair to employ a plurality of processor cores.5
Answer 6.
The rejection of Claims 30, 31, 33-37, and 57-59 over Wright in view of
Nair is therefore reversed.
F. THE REJECTION OF CLAIMS 32 AND 60 OVER WRIGHT
IN VIEW OF NAIR AND FURTHER IN VIEW OF BENNETT
Claims 32 and 60 depend indirectly on independent Claims 30 and 57,
respectively.
The above-noted deficiency in Nair and Wright regarding the use of an
embedded code packet in a serial data stream to configure at least part of a protocol
processing operation being performed on the serial data stream is not cured by the
subject matter relied on in Bennett by the Examiner. The Examiner cited Bennett
as evidence of the obviousness of using different processors to perform different
parts of a protocol processing operation. Answer 10.
The rejection of Claims 32 and 60 over Wright in view of Nair and further in
view of Bennett is therefore reversed.

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G. THE REJECTION OF CLAIMS 38-40 OVER WRIGHT
IN VIEW OF NAIR AND FURTHER IN VIEW OF BROWN
Claims 38-40 depend indirectly on independent Claim 30.
The above-noted deficiency in Nair and Wright regarding using an
embedded code packet in a serial data stream to configure at least part of a protocol
processing operation being performed on the serial data stream is also not cured by
the subject matter relied on in Brown by the Examiner. Brown is cited by the
Examiner as evidence of the obviousness of modifying Nair to employ parallel-
connected microprocessor cores. Answer 11.
As a result, the rejection of Claims 38-40 over Wright in view of Nair and
further in view of Brown is reversed.
H. THE REJECTION OF CLAIMS 41-48 BASED
ON NAIR, OLIVER, AND WRIGHT
This ground of rejection is reversed because Claims 41-48 are indefinite for
the reasons given below in the new ground of rejection under 35 U.S.C. § 112,
second paragraph. See In re Steele, 305 F.2d 859, 862-63, 134 USPQ 292, 295
(CCPA 1962) (Board erred by relying on speculation as to meaning of claim in
affirming rejection under 35 U.S.C. § 103).
I. THE REJECTION OF CLAIMS 46-48 BASED ON
NAIR, OLIVER, WRIGHT, AND BENNETT
This rejection is reversed for the same reason given above in the discussion
of the rejection of Claims 41-48.

5 Plural processor cores are required by Claim 30 but not by Claim 57.
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J. THE REJECTION OF CLAIMS 49-64 BASED
ON NAIR, OLIVER, WRIGHT, AND BROWN
This ground of rejection is reversed as to Claims 49-51 for the reasons given
above. The rejection is likewise reversed as to Claims 61-64 because they are
indefinite for the reasons given below in the new ground of rejection under § 112,
second paragraph. Steele, 305 F.2d at 862-63, 134 USPQ at 295.
The rejection is also reversed as to independent Claims 52 and 57 and their
dependent Claims 53-56 and 58-60. Claim 52, like independent Claim 57, calls for
using an embedded code packet in a serial data stream to configure at least part of a
protocol processing operation being performed on the serial data stream. As
explained above, Nair’s above-noted failure to disclose such a teaching is not
remedied by Wright or Brown. Nor is it remedied by the subject matter relied on
in Oliver by the Examiner. The Examiner cited Oliver as disclosing determining
whether a code packet is embedded in a serial data stream. Answer 13.
K. NEW REJECTION OF CLAIMS 41-51 AND 61-64
UNDER 35 U.S.C. § 112, SECOND PARAGRAPH
Pursuant to our authority under 37 C.F.R § 41.50(b) to enter new grounds of
rejection, we are rejecting independent Claims 41 and 61 and their dependent
Claims 42-51 and 62-64 under 35 U.S.C. § 112, second paragraph, as being
indefinite. Claim 41 reads:
41. A communication protocol processor, comprising:
an interface port; and
a first plurality of microprocessor cores connected in
series to receive a serial data stream from said interface port and
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to perform a protocol processing operation upon said serial data
stream;
wherein a first one of said first plurality of
microprocessor cores is configured to determine whether a code
packet is embedded in said serial data stream, to perform a first
part of said protocol processing operation upon said serial data
stream, and if a code packet is not embedded in said serial data
stream, to transmit a resultant serial data stream of said first part
directly to a second one of said first plurality of microprocessor
cores; and
wherein said second one of said first plurality of
microprocessor cores is configured to perform a second part of
said protocol processing operation upon said resultant serial
data stream.
This claim is clear in some respects and unclear in others. The claim clearly
calls for the first and second microprocessor cores to perform first and second
parts, respectively, of a protocol processing operation on a serial data stream that
may include an embedded code packet. It is also calls for the first microprocessor
core to be configured (i.e., designed) to detect “a code packet” in the serial data
stream. See Specification at page 18, lines 20-21 (“Each microprocessor core 48
includes circuitry to recognize the occurrence of opening field flag 62 of a code
packet 60 conveyed along the transmit serial data path.”).
What is not clear is what is meant by the requirement that the first
microprocessor core “transmit a resultant serial data stream of said first part [of
said protocol processing operation] directly to” the second microprocessor core “if
a code packet is not embedded in said serial data stream.” The meaning of
“directly” in this context is not understood. Is it a temporal or a structural term?
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Also, is this language meant to imply that the first microprocessor core does not
transmit the resultant serial data stream directly to the second microprocessor core
if a code packet is embedded in the serial data stream? If so, what is precluded?
Any transmission, or just “direct” transmission? Furthermore, describing
transmission of the resultant serial data stream as dependent on the presence of a
code packet appears to be inconsistent with the Specification, because the resultant
serial data stream output produced by the first microprocessor core is passed on to
the second microprocessor core whether or not the first microprocessor core
detects a code packet. What is not passed on to the second microprocessor core is
a code packet that is detected by and addressed to the first microprocessor core.
Specification at 18, l. 24 to 19, l. 2. However, the claim language does not appear
to be directed to this aspect of the disclosed invention.
Claim 61 is indefinite in the same respects as Claim 41. The indefiniteness
in Claims 41 and 61 is not cured by any of the dependent claims.
L. SUMMARY
All of the Examiner’s rejections under 35 U.S.C. § 103(a) are reversed. We
have entered a new ground of rejection of Claims 41-51 and 61-64 under 35 U.S.C.
§ 112, second paragraph.
M. APPELLANTS' OPTIONS FOR RESPONDING TO
THE NEW GROUND OF REJECTION
Appellants’ options for responding to the new ground of rejection are set
forth in 37 C.F.R. § 41.50(b) (2006):
(b) . . . A new ground of rejection pursuant to this paragraph
shall not be considered final for judicial review. When the Board
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makes a new ground of rejection, the appellant, within two months
from the date of the decision, must exercise one of the following two
options with respect to the new ground of rejection to avoid
termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the proceeding
will be remanded to the examiner. The new ground of rejection
is binding upon the examiner unless an amendment or new
evidence not previously of record is made which, in the opinion
of the examiner, overcomes the new ground of rejection stated
in the decision. Should the examiner reject the claims,
appellant may again appeal to the Board pursuant to this
subpart.
(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same record. The
request for rehearing must address any new ground of rejection
and state with particularity the points believed to have been
misapprehended or overlooked in entering the new ground of
rejection and also state all other grounds upon which rehearing
is sought.
(Bolding added.)

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No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. §§ 41.50(f) and
41.52(b).
REVERSED; 37 C.F.R. § 41.50(b) 4
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rwk

Robert C. Kowert
Meyertons, Hood, Kivlin, Kowert, & Goetzel
P.O. Box 398
Austin, TX 78767-0398