Ex Parte Pratt

Patent Trial and Appeal Board

Oct 10, 2018

13914970 (P.T.A.B. Oct. 10, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/914,970 06/11/2013
21186 7590 10/12/2018
SCHWEGMAN LUNDBERG & WOESSNER, P.A.
P.O. BOX 2938
MINNEAPOLIS, MN 55402
UNITED ST A TES OF AMERICA
Patrick Pratt
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
13641/471701 7478
EXAMINER
AHN,SUNGS
ART UNIT PAPER NUMBER
2631
NOTIFICATION DATE DELIVERY MODE
10/12/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@slwip.com
SLW@blackhillsip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PATRICK PRATT
Appeal2018-004149
Application 13/914,970 1
Technology Center 2600
Before MARC S. HOFF, JOHN P. PINKERTON, and
SCOTT B. HOWARD Administrative Patent Judges.
HOFF, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134 from a Final Rejection of
claims 5, 6, 12, 14-18, and 21-24. 2 We have jurisdiction under 35 U.S.C.
§ 6(b ).
We reverse.
Appellant's invention is a system and method for reduced bandwidth
digital predistortion. A predetermined nonlinearity may be introduced at an
1 The real party in interest is Analog Devices Global. App. Br. 2.
2 Claims 1-4 and 20 have been cancelled. Claims 7-11, 13, and 19 have been
indicated to be allowable if rewritten in independent form.
Appeal2018-004149
Application 13/914,970
output of a digital predistorter. The application of the nonlinearity to the
predistorter output may expand a bandwidth of the predistorter output from a
first, lower bandwidth to a second, higher bandwidth of a power amplifier
that may be needed to support a predetermined data transfer rate at an RF
transmitter. Spec. ,r 11.
Claim 5 is reproduced below:
5. A predistortion device that forms a wider bandwidth signal using a
nonlinear combination of predistorted bandwidth signals that are narrower
than the wider bandwidth signal, comprising:
a plurality of digital predistortion circuits coupled in parallel to a
digital input signal, each digital predistortion circuit introducing an inversely
modeled gain and phase characteristic of a radio power amplifier into its
respective received digital input signal, each digital predistortion circuit of
the plurality of digital predistortion circuits is connected to receive the
digital input signal, wherein:
an input to the radio power amplifier has a predetermined bandwidth,
an output of each digital predistortion circuit is at a narrower bandwidth than
the predetermined bandwidth, and at least one of the digital predistortion
circuits forms its output by introducing a nonlinear term into the digital input
signal;
a plurality of digital to analog converters, each coupled to a respective
digital predistortion circuit to generate a plurality of analog converted
outputs; and
an analog mixer coupled to each of the digital to analog converters,
wherein the analog mixer mixes the plurality of analog converted outputs of
the digital predistortion circuits together to generate, as the input to the radio
power amplifier, a nonlinear signal using a nonlinear combination of the
plurality of analog converted outputs, and wherein the nonlinear combining
operates to widen a bandwidth of the plurality of analog converted outputs
by generating a higher order distortion term from terms introduced by the
2
Appeal2018-004149
Application 13/914,970
digital predistortion circuits, such that the nonlinear signal has the
predetermined bandwidth. See App. Br., Claims Appendix, 18.
The Examiner relies upon the following prior art in rejecting the
claims on appeal:
Hongo et al., US 2003/0053552 Al Mar. 20, 2003;
hereinafter "Hongo";
Ziegler et al., US 2008/0218262 Al Sept. 11, 2008;
hereinafter "Ziegler";
Anvari et al., US 2013/0307618 Al Nov. 21, 2013;
hereinafter "Anvari"·
'
Kim et al., US 2002/0034260 Al Mar. 21, 2002;
hereinafter "Kim"
Claims 5, 6, 12, 14-18, 21, and 23 stand rejected under 35 U.S.C.
§ I03(a) as being unpatentable over Hongo, Ziegler, and Anvari. See Final
Act. 4-15.
Claims 22 and 24 stand rejected under 35 U.S.C. § I03(a) as being
unpatentable over Hongo, Ziegler, Anvari, and Kim. See Final Act. 15-16.
Throughout this decision, we make reference to the Final Office
Action, mailed Apr. 7, 2017 ("Final Act."), Appeal Brief ("App. Br.," filed
Oct. 9, 2017), the Reply Brief ("Reply Br.," filed Mar. 12, 2018), and the
Examiner's Answer ("Ans.," mailed Jan. 24, 2018) for their respective
details.
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Appeal2018-004149
Application 13/914,970
ISSUE
Does the combination of Hongo, Anvari, and Ziegler teach or suggest
a plurality of digital predistortion circuits coupled in parallel to a digital
input signal, each digital predistortion circuit being connected to receive the
digital input signal?
ANALYSIS
CLAIMS 5, 6, 12, 14-18, 21, AND 23
Independent claims 5 and 14 recite that "each digital predistortion
circuit of the plurality of digital predistortion circuits is connected to receive
the digital input signal." Independent claim 18 recites "separately applying
the inversely modeled gain and phase characteristics at each of the narrower
bandwidths to a digital input signal, thereby forming a plurality of
predistorted signals, wherein at least one of the applying steps includes
introducing a nonlinear term into the digital input signal."
The Examiner finds that Hongo teaches these limitations. The
Examiner cites Figure 1 of Hongo, and the inputs to each predistortion unit
(PD unit 1, PD unit 2, ... , PD unit n) of distortion compensator 2 of Hongo.
Final Act. 5.
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Appeal2018-004149
Application 13/914,970
We agree with Appellant that the Examiner erred in so finding.
Figure 1 of Hongo is reproduced below:
Fig.l
Figure 1 is a block diagram showing the configuration of an amplifier device
incorporating a first embodiment of the invention. Hongo ,r 113.
We agree with Appellant that none of the PD units of Hongo receives
the input signal. App. Br. 10. Rather, the input signal is provided to
frequency band divider 1, which generates distinct frequency band signals
fl -fn. Id. The frequency band signals, rather than "the digital input signal,"
are provided as inputs to the predistortion (PD) units. Id.
We do not agree with the Examiner's response that "Hongo disclose
[sics] the same input signal being fed to the distortion compensator." Ans.
3. Hongo discloses that "the signal to be amplified ( object signal) is a signal
containing multiple frequency band signals and distortion compensation is
conducted separately for each frequency band signal." Hongo ,r 50.
Therefore, it is clear that the PD units of Hongo do not each conduct
distortion compensation on "the digital input signal" as claimed, but on one
particular frequency band signal (i.e., one of signals fl-fn) each.
We find that the Examiner's combination fails to teach all the
limitations of independent claims 5, 14, and 18. Therefore, we do not sustain
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Appeal2018-004149
Application 13/914,970
the Examiner's§ 103(a) rejection of claims 5, 6, 12, 14--18, 21, and 23 as
being unpatentable over Hongo, Anvari, and Ziegler.
CLAIM 22 AND 24
Claim 22 depends from independent claim 5, and claim 24 depends
from independent claim 18. We have reviewed Kim, and we find that Kim
does not remedy the deficiencies identified supra with respect to the
rejection of claims 5 and 18. Accordingly, we do not sustain the Examiner's
§ 103(a) rejection of claims 22 and 24, for the reasons expressed supra with
respect to claims 5 and 18.
CONCLUSION
The combination of Hongo, Anvari, and Ziegler does not teach or
suggest a plurality of digital predistortion circuits coupled in parallel to a
digital input signal, each digital predistortion circuit being connected to
receive the digital input signal.
ORDER
The Examiner's decision to reject claims 5, 6, 12, 14--18, and 21-24
under 35 U.S.C. § 103(a) is reversed.
REVERSED
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