Ex Parte Perkins

Patent Trial and Appeal Board

Sep 19, 2018

14608809 (P.T.A.B. Sep. 19, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/608,809 01/29/2015
144019 7590 09/21/2018
Broadcom Limited
One Freedom Square
11951 Freedom Drive, 13th Floor
Reston, VA 20191
FIRST NAMED INVENTOR
Nathan Perkins
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2014-138USORG 2523
EXAMINER
KIM, TONG-HO
ART UNIT PAPER NUMBER
2811
NOTIFICATION DATE DELIVERY MODE
09/21/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
cjohnson@volentine.com
iplaw@volentine.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte NATHAN PERKINS
Appeal2018---000722
Application 14/608,809
Technology Center 2800
Before CATHERINE Q. TIMM, N. WHITNEY WILSON, and MERRELL
C. CASHION JR, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL 1
1 In explaining our Decision, we cite to the Specification of January 29, 2015
(Spec.), Final Office Action of May 20, 2016 (Final), Advisory Action of
September 12, 2016 (Advisory), Appeal Brief of February 28, 2017 (Appeal
Br.), Examiner's Answer of August 28, 2017 (Ans.), and Reply Brief of
October 30, 2017 (Reply Br.).
Appeal2018---000722
Application 14/608,809
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § I34(a), Appellant2 appeals from the
Examiner's decision to reject claims 1-22 under 35 U.S.C. § 103 as obvious
over Chen3 in view ofHill. 4 We have jurisdiction under 35 U.S.C. § 6(b). 5
We AFFIRM.
The claims are directed to an apparatus including a first heat sink (see,
e.g., Figure 2 at 204) over a multilayer package substrate (205). Spec. ,r 280.
Figure 2 depicts an embodiment of the apparatus and is reproduced below: 6
2 Appellant is the applicant, Avago Technologies General IP (Singapore)
PTE., Ltd., Inc., which is identified as the real party in interest. Appeal Br.
3.
3 Chen et al., US 2009/01793324 Al, published July 16, 2009.
4 Hill, US 5,710,068, issued Jan. 20, 1998.
5 Appellant argues that the final rejection was improperly made final.
Appeal Br. 11. We do not have jurisdiction to review the finality of a
rejection. Such a question is a petitionable matter. MPEP § 1201. Thus, we
do not address this question.
6 We reproduce Figure 2 as filed January 29, 2015, but with corrected
reference number 205. We reproduce the original figure with the correction
because the copy of the replacement figure located in the electronic file is of
poorer quality than the original.
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Appeal2018---000722
Application 14/608,809
~221
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200
221 .J"1 ~217 I
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102
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Figure 2 is a cross-section view of a semiconductor structure
The multilayer package substrate 205 includes a second heat sink 212.
Spec. ,r 320, Fig. 2. The second heat sink 212 is disposed in the substrate's
first layer 206, second layer 207, and third layer 208, which are
distinguished by dashed-lines in Figure 2. Spec. ,r,r 280, 360, Fig. 2.
Specifically, second heat sink 212 includes a first electrically conductive
layer 213 disposed in the first layer 206, a second electrically conductive
layer 214 disposed in the third layer 208 and vias 215 disposed therebetween
in the second layer 207. Spec. ,r 320.
We reproduce claim 1, with reference numerals from Figure 2 and
with key limitations at issue highlighted:
1. An apparatus, comprising:
a first heat sink [204] disposed over a multilayer package
substrate [205], the first heat sink [204] configured to connect
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Appeal2018---000722
Application 14/608,809
to a semiconductor device [202] and to provide an electrical
ground for the semiconductor device [202],
the multilayer package substrate [205] comprising:
a second heat sink [212] comprising a first
electrically conductive layer [213] disposed in a first
layer [206];
a second electrically conductive layer [214]
disposed in a third layer [208]; and
a via [215 J disposed in a second layer [207], the
via [215] electrically connecting the first electrically
conductive layer [213 J and the second electrically
conductive layer [214],
wherein the first heat sink [204] overlaps substantially all
of the first electrically conductive layer [213] and no dielectric
material exists in the multilayer package substrate [205] in a
region of contact [217] of the first heat sink [204] and the first
electrically conductive layer [213].
Appeal Br. 14 ( claims appendix).
OPINION
Appellant focuses on the Examiner's rejection of claims 1 and 10, the
independent claims, and argues the rejection of claims 6 and 19 as a separate
group. Appeal Br. 6-11. We select claims 1 and 6 as representative for
resolving the issues on appeal.
Claim 1
For claim 1, the issue on appeal is: Has Appellant identified a
reversible error in the Examiner's finding that Chen teaches a second heat
sink having the structure required by claim 1, specifically, the first
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Application 14/608,809
electrically conductive layer disposed in a first layer and a via disposed in a
second layer?
Appellant has not identified such an error.
The Examiner finds Chen teaches a multilayer package substrate (56,
66, 61, 62) having a second heat sink (66, 62). Final 3. To support this
finding, the Examiner points to Chen's Figure 9 and related disclosure. Id.
Chen's Figure 9 is reproduced below:
26 66 65 26
\ I
-------28
26
Chen's Figure 9 is a cross-sectional view of an integrated circuit package
Chen describes the package of Figure 9 along with a number of other
embodiments and depicts these embodiments in Figures 6 through 10. Chen
,r 55. In these embodiments, heat dissipation layers are formed around a
substrate (substrate 60 in Fig. 6, substrate 61 in Figs. 7-10) so that the heat
dissipation layer passes through a hole (Fig. 6) or holes (Figs. 7-10) in the
substrate and extends on both sides of the substrate. Chen ,r,r 56-60, Figs. 6-
10. On the upper side of the substrate, the heat dissipation layer contacts a
conductive line 56. Chen ,r 56. In the embodiment of Figure 9, heat
dissipation layer 66 is the layer that contacts conductive line 56. Chen Fig.
9.
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Appeal2018---000722
Application 14/608,809
In the Final Office Action, the Examiner finds Chen's conductive
layer 66 is the "first electrically conductive layer disposed in a first layer"
and the material within the open area of substrate 61 is the "via disposed in a
second layer" recited in claim 1. Final 3.
Appellant contends that the Examiner is relying on one and the same
element of Chen (66) for two features, i.e., for both the first conductive layer
and the first layer. Appeal Br. 8; Reply Br. 2-3. But the argument fails
because Chen's Figure 9 plainly depicts the location of heat dissipation layer
66 as in the same location as Appellant's first electrically conductive layer
213. Compare Chen's Fig. 9 (layer 66), with Appellant's Fig. 2 (conductive
layer 213). The heat dissipation layer 66 extends over the substrate 61 so
that it is disposed in a first layer located on top of the substrate just as
Appellant's first conductive layer 213 extends in a first layer 206 that resides
in the upper region of the multilayer package substrate. Appellant does not
use the term "first layer" to denote a separate element, but rather to define an
upper region of the multilayer package substrate. See Appellant's Fig. 2
( dashed lines defining first layer 206) and Spec. ,r 280 ( explaining that the
dashed-lines distinguish boundaries for layers 206, 207, 208, and these
layers may comprise a dielectric layer, electrical elements, or both). Chen's
layer 66 is in the designated upper region.
Appellant's argument regarding the vias is not understood. Appeal
Br. 9; Reply Br. 3--4. As found by the Examiner, Chen's heat dissipation
material, shown with "+" symbols in Figure 9, extends through holes in
substrate 61. Contrary to Appellant's argument, the heat dissipation material
connects the layer 66 material above and the layer 62 material below and
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Application 14/608,809
electrically connects layers 66 and 62 as required by claim 1. Chen Fig. 9.
Appellant has not adequately explained how the claimed arrangement differs
from the one disclosed by Chen.
Thus, Appellant has not identified a reversible error in the Examiner's
finding that Chen teaches a second heat sink having the structure required by
claim 1.
Claims 6 and 19
Claim 6 requires the semiconductor device comprises a plurality of
semiconductor devices, and "the first heat sink comprises a plurality of
pedestals, each pedestal being configured to connect to one of the
semiconductor devices." Claim 19, which stands or falls with claim 6,
recites a similar limitation.
Appellant assumes for argument sake but does not concede that
bonding pads 26 and third heat dissipation layer 65 of Chen are pedestals.
Appeal Br. 10-11. Appellant, however, does not provide any basis to
support a finding that bonding pads 26 are structurally different from the
pedestals of the claim. Instead, Appellant argues that "there is no disclosure
whatsoever in Chen that the bonding pads 26 and heat dissipation layer 65
are connected in a one-to-one manner with semiconductor devices." Appeal
Br. 11 ( emphasis added).
As pointed out by the Examiner, claim 6 does not require the
pedestals be connected one-to-one to separate semiconductor devices.
Claim 6 recites "each pedestal being configured to connect to one of the
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Application 14/608,809
semiconductor devices." The language of the claim is broad enough to
encompass using multiple pedestals to connect to one semiconductor device.
Because claims 6 and 19 are broader than would be required by
Appellant's argument, Appellant has not identified a reversible error in the
Examiner's rejection of claims 6 and 19.
Chen.
CONCLUSION
We sustain the Examiner's rejection of claims 1-22 as obvious over
DECISION
The Examiner's decision is affirmed.
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l).
AFFIRMED
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