Ex Parte Pennock et al

Patent Trial and Appeal Board

Jan 15, 2013

11771743 (P.T.A.B. Jan. 15, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/771,743 06/29/2007 James D. Pennock HARM0154PUSP1 8434
109676 7590 01/16/2013
Brooks Kushman P.C./Harman
1000 Town Center
Twenty Second Floor
Southfield, MI 48075
EXAMINER
HASSAN, AURANGZEB
ART UNIT PAPER NUMBER
2184
MAIL DATE DELIVERY MODE
01/16/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
_____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_____________

Ex parte JAMES D. PENNOCK, RONALD BAKER,
BRIAN R. PARKER, and CHRISTOPHER BELCHER
_____________

Appeal 2011-003778
Application 11/771,743
Technology Center 2100
______________

Before ROBERT E. NAPPI, HUNG H. BUI, and LYNNE E. PETTIGREW,
Administrative Patent Judges.

ROBERT E. NAPPI, Administrative Patent Judge

DECISION ON APPEAL
Appeal 2011-003778
Application 11/771,743

2

This is a decision on appeal under 35 U.S.C. § 134(a) of the rejection
of claims 1 through 8 and 10 through 20.
1

We affirm.
INVENTION
The invention is directed to a communications interface which
includes a set of memory spaces whichto alternately interface with a
processor or a serial controller. See paragraphs 0007-0009 of Appellants’
Specification. Claim 1 is representative of the invention and reproduced
below:
1. A serial communication interface engine, comprising:
a processor;
a communication subsystem comprising an advance
register;
a first buffer memory;
a second buffer memory; and
a swap controller operable to alternately swap access to
the first buffer memory and the second buffer memory between
the processor and the communication subsystem;
where the advance register is operable to duplicate data
written to a predetermined location of the first buffer memory
when the first buffer memory is accessible to the processor.

1
Appellants have indicated that they are not appealing the rejection of claim
21 and have expressed the desire to cancel the claim. Brief 3. Further,
while the Examiner has not withdrawn the rejection of this claim it is also
not addressed in the Examiner’s Answer. Accordingly, the rejection of this
claim is not before us.
Appeal 2011-003778
Application 11/771,743

3

REJECTIONS AT ISSUE
The Examiner has rejected claims 1 through 3 under 35 U.S.C.
§ 102(b) as anticipated by Yoshimura (U.S. Patent 6,421,274 B1). Answer
4-5.
2

The Examiner has rejected claims 4 through 8, and 10 through 20
under 35 U.S.C. § 103(a) as unpatentable over Yoshimura and Hall (U.S.
Patent 5,581,779). Answer 5-9.

ISSUE
Appellants argue on pages 8 through 10 of the Appeal Brief that the
Examiner’s rejection of claims 1 through 3 under 35 U.S.C. § 102(b) is in
error.
3
These arguments present us with the issue: did the Examiner err in
finding that Yoshimura teaches a controller to alternatively swap access to
the first buffer memory and the second buffer memory between the
processor and communications subsystem as recited in representative claim
1?
Appellants’ argue on page 11 of the Brief that the rejection under 35
U.S.C. § 103(a) based upon Yoshimura and Hall is in error for the same
reason as discussed with respect to claim 1. Accordingly, Appellants’
arguments directed to the Examiner’s rejection under 35 U.S.C. § 103(a) do
not present us with any additional issues.

2
Throughout this opinion we refer to the Examiner’s Answer mailed on
August 30, 2010.
3
Throughout this opinion we refer to Appellants’ Appeal Brief filed on
June 17, 2010.
Appeal 2011-003778
Application 11/771,743

4

ANALYSIS
We have reviewed Appellants’ arguments in the Brief, the Examiner’s
rejection and the Examiner’s response to the Appellants’ arguments. We
disagree with Appellants’ conclusion that the Examiner erred in finding that
Yoshimura teaches a controller to alternatively swap access to the first
buffer memory and the second buffer memory between the processor and
communications subsystem. The Examiner has provided a comprehensive
response to this issue in the Answer. In particular, the Examiner has found
that Yoshimura teaches two memory locations R1 and R2 (see Figure 1)
which are alternately connected to a processor or a memory control
subsystem. Answer 10-11.
We concur with the Examiner’s finding and note that Figures 2A, 2B,
7A, 7B and the accompanying text in Yoshimura provide an example of the
alternate access to the memory locations R1 and R2. Based upon these
findings, the Examiner concludes that the argued limitation is taught by
Yoshimura. We concur with the Examiner’s conclusions in the Answer and
adopt them as our own. Accordingly, we sustain the Examiner’s rejection
under 35 U.S.C. § 102(b) and 35 U.S.C. § 103(a).

ORDER
The decision of the Examiner to reject claims 1 through 8 and 10
through 20 is affirmed.
Should there be further prosecution of this application, the Examiner
should cancel claim 21 in accordance with Ex Parte Ghuman, No. 2008-
1175, 2008 WL 2109842 (BPAI May 1, 2008) (precedential) and MPEP
1215.03.
Appeal 2011-003778
Application 11/771,743

5

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

ELD