Ex Parte PawlowskiDownload PDFPatent Trial and Appeal BoardFeb 10, 201512350136 (P.T.A.B. Feb. 10, 2015) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/350,136 01/07/2009 J. Thomas Pawlowski 2008-0377 (MICS:0277) 6331 52142 7590 02/11/2015 FLETCHER YODER (MICRON TECHNOLOGY, INC.) P.O. BOX 692289 HOUSTON, TX 77269-2289 EXAMINER DANG, KHANH ART UNIT PAPER NUMBER 2111 MAIL DATE DELIVERY MODE 02/11/2015 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte J. THOMAS PAWLOWSKI ____________________ Appeal 2012-011052 Application 12/350,136 Technology Center 2100 ____________________ Before STANLEY M. WEINBERG, JOHNNY A. KUMAR, and JON M. JURGOVAN, Administrative Patent Judges. JURGOVAN, Administrative Patent Judge. DECISION ON APPEAL Appellant 1 appeals under 35 U.S.C. § 134(a) from a rejection of claims 1-13 and 45-48. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 2 1 The real party in interest is Micron Technology, Inc. 2 Our Decision refers to the Appeal Brief filed April 2, 2012 (“App. Br.”), the Examiner’s Answer mailed May 25, 2012 (“Ans.”), the Reply Brief filed July 25, 2012 (“Reply Br.”), and the Specification filed January 7, 2009 (“Spec.”). Appeal 2012-011052 Application 12/350,136 2 CLAIMS SUMMARY The claims are directed to systems comprising a pattern-recognition processor, a processing unit, and a memory (Spec. Abstract). The claims also recite a pattern-recognition bus and a memory bus. Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A system, comprising: a pattern-recognition processor; a processing unit (PU) coupled to the pattern-recognition processor via a pattern-recognition bus; and memory coupled to the PU via a memory bus, wherein the pattern- recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively, and wherein a portion of the pattern-recognition bus serves at least one different function compared to a corresponding portion of the memory bus. Thus, claim 1 recites a portion of the pattern-recognition bus serves at least one different function compared to a corresponding portion of the memory bus. Dependent claim 2 recites that the pattern-recognition bus forms at least one more connection than the memory bus. Dependent claim 8 recites that a portion of the pattern-recognition bus serves at least one different function compared to the corresponding portion of the memory bus and the function varying based on the mode of operation of the pattern-recognition processor. Independent claim 45 is similar to claim 1 but recites the pattern- recognition processor is configured to interpret at least some signals on the pattern-recognition bus differently than from their function on the memory bus. Dependent claim 48 recites that the pattern-recognition bus and the memory bus are independent of one another. Appeal 2012-011052 Application 12/350,136 3 REJECTIONS The Examiner made the following rejections: 1. Claims 1-6, 8-11, 13, and 45-48 stand rejected under 35 U.S.C. § 102(b) based on Arnold 3 (Ans. 5). 2. Claim 7 stands rejected under 35 U.S.C. § 103(a) based on Arnold in view of well-known prior art (Ans. 10). 3. Claim 12 stands rejected under 35 U.S.C. § 103(a) based on Arnold in view of well-known prior art (Ans. 11). ANALYSIS Claims 1 and 45 A. Independent Buses Argument Appellant argues that Arnold fails to disclose a pattern-recognition bus and a memory bus as recited in claims 1 and 45 (App. Br. 5-6; Reply Br. 3-4). Specifically, Appellant argues these buses are described in the Specification as independent from one another, whereas, in Arnold, the memory 18 and data pattern monitor 12 are both connected to the same internal buses 66 (for control words), 68 (for addresses), and 56 (for data words)(id.). The Examiner contends claims 1 and 45 do not recite that the buses are “independent” from one another (Ans. 13). We agree with the Examiner that claims 1 and 45 do not recite the two buses are independent from one another. As such, Appellant’s arguments are not commensurate in scope with the claims. We also note the Examiner’s citation to the Specification, paragraph 70, where it is stated that the memory bus and 3 US 6,279,128 B1 issued Aug. 21, 2001. Appeal 2012-011052 Application 12/350,136 4 pattern-recognition bus may be the same (see Ans. 14). Accordingly, we are not persuaded the Examiner erred in the rejection on this ground. B. Different Function/Interpretation Argument Appellant also argues Arnold fails to disclose a portion of the pattern- recognition bus serving at least one different function compared to a corresponding portion of the memory bus, as recited in claim 1 (App. Br. 6-7; Reply Br. 2, 5). Similarly, for claim 45, Appellant argues Arnold fails to disclose the pattern-recognition processor is configured to interpret at least some signals on the pattern-recognition bus differently than from their function on the memory bus (id.). To the contrary, the Examiner finds the functions of the signals on Arnold’s memory bus connecting DRAM memory 18 to CPU 14 are addressing function, commanding function, and data read/write function according to DRAM standard protocol (Ans. 19-21). The Examiner also finds the same signals on the memory bus are passed to pattern-recognition processor 12 via the pattern-recognition bus, which interprets such signals as patterns and performs the function of detecting and recognizing the patterns (id.)(see also Ans. 15-16 citing Arnold Fig. 2 showing memory bus and pattern-recognition bus). We agree with the Examiner that these features of claims 1 and 45 are taught by Arnold for the reasons stated by the Examiner. Specifically, Arnold’s pattern-recognition bus performs a different function than the memory bus identified by the Examiner, and signals on those buses are interpreted differently by the memory 18 and data pattern monitor 12. Accordingly, we are not persuaded the Examiner erred in making the rejection on this ground. Appeal 2012-011052 Application 12/350,136 5 C. Same Signals Argument Appellant states Arnold discloses that the internal buses 66, 68, 56 connected to both the memory 18 and data pattern monitor 12 receive the same signals and information (App. Br. 7; Reply Br. 4). According to Appellant, the Examiner has not shown Arnold’s memory 18 and monitor 12 ever receive different information on the buses (id.). Therefore, Appellant argues that Arnold cannot be read as disclosing a pattern-recognition bus that serves at least one different function or a pattern-recognition processor that interprets at least some signals differently from their function on the memory bus, as recited in claims 1 and 45 (id.). On this point, the Examiner disagrees, finding claims 1 and 45 do not recite that the memory and pattern-recognition processor receive different information relative to each other (Ans. 19-20). We agree with the Examiner that claims 1 and 45 do not recite this limitation, and that Appellant’s arguments are not commensurate in scope with the claim. Accordingly, we are not persuaded the Examiner erred. D. DRAM Bus Argument Appellant also argues the Examiner has incorrectly assumed that because a DRAM memory bus is a defined and well-known bus, Arnold must disclose a bus that is independent and that Arnold must disclose a pattern-recognition bus that is different and independent from the DRAM bus (App. Br. 7). Appellant argues this cannot be true of Arnold, because internal buses 66, 68, and 56 cannot be considered both the memory bus and pattern-recognition bus, which is a rephrasing of the independent buses argument previously discussed (id.). In addition, the Appellant again argues Arnold’s memory bus and pattern-recognition bus as described by the Examiner cannot serve functions or interpret data differently because they Appeal 2012-011052 Application 12/350,136 6 carry the same signals, which is a rephrasing of the same signals argument previously discussed (id.). For the reasons previously explained with respect to the independent buses and same signals arguments, we are not persuaded the Examiner erred in the rejection on this ground. E. Super-Set Argument Appellant argues the Examiner takes the view that in Arnold the memory bus is a super-set of the pattern-recognition bus whereas claims 1 and 45 implicitly recite that the pattern-recognition bus is a super-set of the memory bus (App. Br. 8; Reply Br. 3-4). The Examiner finds there is no limitation in claims 1 and 45 indicating the pattern-recognition bus is a super-set of the memory bus (Ans. 25). We agree with the Examiner that claims 1 and 45 recite no such limitation. As Appellant’s argument is not commensurate in scope with the claims, we are not persuaded that the Examiner erred in the rejection on this ground. Claim 2 Claim 2 recites that the pattern-recognition bus forms at least one more connection than the memory bus. Appellant argues Arnold discloses no such feature (App. Br. 8-9; Reply Br. 5-6). Specifically, Appellant argues Arnold’s buses 56, 66, 68 are connected to both the memory 18 and data pattern monitor 12 and would appear to have the same number of connections (App. Br. 9). The Examiner finds the CPU interrupt on internal bus 90, which is presented to monitor controller 70 for transfer to CPU 14 by way of internal bus 66 is the claimed “at least one more connection” (Ans. 26-28 citing Arnold, col. 7, ll. 47-58). As the Examiner’s finding is reasonable, we sustain the Examiner’s rejection of claim 2. Appeal 2012-011052 Application 12/350,136 7 Claim 8 Claim 8 recites that a portion of the pattern-recognition bus serves at least one different function compared to the corresponding portion of the memory bus and the function varying based on the mode of operation of the pattern-recognition processor. Appellant argues that the Examiner has not shown the function varying based on the mode of operation of the pattern- recognition processor (App. Br. 9-10; Reply Br. 6-7). The Examiner finds that when the address signal carries address data, the pattern-recognition processor (i.e., Arnold’s data pattern monitor 12) is in a first mode; when the address signal carries a command, the pattern- recognition processor is in a second mode; and when the address signal carries register select, the pattern-recognition processor is in a third mode (App. Br. 8, 29-30). The Examiner further finds that according to the DRAM standard, the address signal carries A0-A11 and BA0, BA1; A0-A11 includes row/column address inputs; BA0, BA1 are select input command for selecting which memory bank is to be active; and A0 –A11 and BA0, BA1 are used to select an operation mode in the mode register (id.). Accordingly, the Examiner concludes the limitations of claim 8 are met by these teachings. We agree with the Examiner that the teachings of Arnold and the DRAM standard are sufficient to teach the limitations of claim 8 for the reasons stated by the Examiner. Thus, we sustain the Examiner’s rejection on this ground. Claim 48 Claim 48 recites that the pattern-recognition bus and the memory bus are “independent” of one another. Appellant argues Arnold’s memory 18 and data pattern monitor 12 are both connected to the same internal buses Appeal 2012-011052 Application 12/350,136 8 66, 68, and 56 and thus could not be independent of one another (App. Br. 11-12 citing Arnold col. 5, l. 47 – col. 6, l. 45; Figs. 2, 3). The Examiner finds that the pattern-recognition bus and memory bus of Arnold are functionally independent from one another because the functions of signals with respect to the memory and pattern-recognition processor are different, and because each interprets the signals differently (Ans. 30-32). In addition, the Examiner finds that the pattern-recognition bus and memory bus of Arnold are physically independent of one another (id.). Although Appellants’ argued “independent” in the context of the claims means “separate” (see App. Br. 5-6), the Examiner has interpreted Arnold’s memory and data pattern monitor buses as “functionally independent” (see Ans. 30-32). During prosecution, claims are given their broadest reasonable interpretation consistent with the specification. In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004). Absent a special definition in the Specification, we give claim terms their ordinary and customary meaning, as would be understood by one of ordinary skill in the art at the time of the invention. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Any special definition for a claim term must be set forth with reasonable clarity, deliberateness, and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). As there is no definition of “independent” in the Specification and claim 48 does not preclude the Examiner’s broadest reasonable interpretation of “independent” to include “functionally independent”, we are not persuaded the Examiner reversibly erred in the rejection of claim 48. Appeal 2012-011052 Application 12/350,136 9 DECISION For the above reasons, the Examiner’s rejection of claims 1-13 and 45-48 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED ELD Copy with citationCopy as parenthetical citation