Ex Parte Obara et al

Board of Patent Appeals and Interferences

Jul 31, 2007

09427114 (B.P.A.I. Jul. 31, 2007)

The opinion in support of the decision being entered today
is not binding precedent of the Board.

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte MITSURU OBARA, KENICHI SAWADA, ATSUSHI
ISHIKAWA, and KAZUHIRO ISHIGURO
____________

Appeal 2007-1509
Application 09/427,114
Technology Center 2100
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Decided: July 31, 2007
____________

Before JOSEPH F. RUGGIERO, ROBERT E. NAPPI, and JOHN A.
JEFFERY, Administrative Patent Judges.

RUGGIERO, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from the Final Rejection of
claims 1-9, 11-19, and 21-26. Claims 10 and 20 have been canceled. We
have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
Appeal 2007-1509
Application 09/427,114

Appellants’ disclosed invention relates to image processing in which a
plurality of processors perform a series of processings on input image data in
a prescribed order with the processings being executed asynchronously by
the plurality of processors. A shared memory is utilized to store image pixel
data to be processed and a state flag is used to represent the state of
processing of the data for each pixel. (Specification 3-4).
Claim 1 is illustrative of the invention and reads as follows:
1. A data processing system comprising:
a plurality of processors for executing a series of different types of
processing functions on data to be processed in a prescribed order, each
processor executing a processing function different from one another and
said data to be processed being image data that consists of a plurality of
pixel data; and
a memory for storing said data to be processed in association with
state information to represent the processing to be performed next for each
pixel data of said data to be processed, wherein
said processing functions are asynchronously executed on said data to
be processed by said plurality of processors, one processing is executed on
each pixel data by one of the processors at a time and said plurality of
processors share said memory.

The Examiner relies on the following prior art references to show
unpatentability:
Orimo US 5,630,135 May 13, 1997
Charles US 5,790,842 Aug. 4, 1998

Free On-Line Dictionary of Computing (FOLDOC), October 21, 1994, web
page available at http//foldoc.doc.ic.ac.uk/foldoc.cgi?query=image, (October
1994).

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Merriam-Webster’s Collegiate Dictionary, Tenth Edition, pages 72 and
1192, (2001).1

Claims 1-9, 11-19, and 21-26, all of the appealed claims, stand
rejected under 35 U.S.C. § 103(a). As evidence of obviousness, the
Examiner offers Orimo in view of Charles with respect to claims 25 and 26,
and adds FOLDOC to the basic combination with respect to claims 1-9, 11-
19, and 21-24.
Rather than reiterate the arguments of Appellants and the Examiner,
reference is made to the Brief and Answer for the respective details. Only
those arguments actually made by Appellants have been considered in this
decision. Arguments which Appellants could have made but chose not to
make in the Brief have not been considered and are deemed waived [see 37
CFR § 41.37(c)(1)(vii)].

ISSUES
(1) Under 35 U.S.C § 103(a), with respect to appealed claims 25 and
26, would one of ordinary skill in the art at the time of the
invention have been motivated and found it obvious to combine
Orimo with Charles to render the claimed invention unpatentable.
(2) Under 35 U.S.C § 103(a), with respect to appealed claims 1-9, 11-
19, and 21-24 would the ordinarily skilled artisan have been
motivated and found it obvious to modify the combination of
Orimo and Charles by adding the FLDOC reference to render the
claimed invention unpatentable.

1 This reference is not included as part of the Examiner’s stated grounds of
rejection but, rather, is cited as evidence in support of the rejection.
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Application 09/427,114

PRINCIPLES OF LAW
In rejecting claims under 35 U.S.C. § 103, it is incumbent upon the
Examiner to establish a factual basis to support the legal conclusion of
obviousness. See In re Fine, 837 F.2d 1071, 1073, 5 USPQ2d 1596, 1598
(Fed. Cir. 1988). In so doing, the Examiner must make the factual
determinations set forth in Graham v. John Deere Co., 383 U.S. 1, 17,
148 USPQ 459, 467 (1966). “[T]he examiner bears the initial burden, on
review of the prior art or on any other ground, of presenting a prima facie
case of unpatentability.” In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ2d
1443, 1444 (Fed. Cir. 1992). Furthermore, “‘there must be some articulated
reasoning with some rational underpinning to support the legal conclusion of
obviousness’ . . . [H]owever, the analysis need not seek out precise teachings
directed to the specific subject matter of the challenged claim, for a court
can take account of the inferences and creative steps that a person of
ordinary skill in the art would employ.” KSR Int’l Co. v. Teleflex Inc., 127
S. Ct. 1727, 1741, 82 USPQ2d 1385, 1396 (2007)(quoting In re Kahn, 441
F.3d 977, 988, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006)).
ANALYSIS
With respect to the Examiner’s obviousness rejection of independent
claims 1 and 11, Appellants’ arguments in response assert a failure to set
forth a prima facie case of obviousness since all of the claim limitations have
not been taught or suggested by the applied prior art references. After
careful review of the disclosures of Orimo, Charles, and FOLDOC in light
of the arguments of record, however, we do not find Appellants’ arguments
to be persuasive.
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Application 09/427,114

Appellants’ arguments do not attack the Examiner’s proposed
combination of Orimo, FOLDOC, and Charles but, rather, focus on the
alleged deficiency of the Orimo reference in disclosing plural processors,
each of which execute a processing function different from one another as
claimed. According to Appellants (Br. 9-10), the processors 12 and 13
(Figure 8) and 11-13 (Figure 10) of Orimo, in contrast, execute multiple
version programs which perform the same function of simulation.
It is apparent from the disclosure of Orimo, however, that Appellants’
arguments overlook the operation of processor 14 illustrated in Figures 8 and
10 of Orimo. As described, for example, at column 8, lines 8-12 and column
10, lines 19-23 of Orimo, the processor 14 receives the results of the
simulation processing in processors 11-13 and performs a different
application program processing utilizing the results of the simulation
processing. That the processing performed by Orimo’s processor 14 is
different from that performed by processors 11-13 is verified by Orimo at
column 11, lines 18-20.
We also find no error, Appellants’ arguments to the contrary
notwithstanding, in the Examiner’s finding (Answer 4) that Orimo’s
processor 14, which receives and executes a second processing after it
receives the results of the first processing from processors 11-13, is
operating asynchronously with respect to processors 11-13. We further
agree with the Examiner (Answer 12) that Orimo discloses that one
processing is executed on each pixel data by one of the processors at a time
as claimed since the claim language does not require that only one
processing is executed at a time.
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For the above reasons, since it is our opinion that the Examiner’s
prima facie case of obviousness has not been overcome by any convincing
arguments from Appellants, the Examiner’s 35 U.S.C. § 103(a) rejection,
based on the combination of Orimo, FOLDOC, and Charles, of independent
claims 1 and 11, as well as dependent claims 2-9, 12-19, and 21-24 not
separately argued by Appellants, is sustained.
Turning to a consideration of the Examiner’s 35 U.S.C. § 103(a)
rejection of appealed independent claims 25 and 26 based on the
combination of Orimo and Charles, we sustain this rejection as well. The
language of claims 25 and 26 differs slightly from that of previously
discussed independent claims 1 and 11 in that there is a requirement that a
second processor execute a second processing on data that was subjected to
a first processing by a first processor.
Similar to Appellants’ arguments directed to independent claims 1 and
11, Appellants’ arguments directed at claim 24 do not attack the Examiner’s
proposed combination of Orimo and Charles but, instead, focus on the
alleged deficiencies of Orimo in disclosing the claimed processing
requirements. We find, however, as did the Examiner (Answer 16), that
Orimo has an explicit disclosure of the processor 14 performing a second
processing on data that was subject to a first processing in processors 11-13.
For example, Orimo discloses (col. 2, ll. 9-16) that, after receiving messages
containing results of the processings by the first processors 11-13, the
second processor, i.e., processor 14, selects a message, and “executes a
program in the second processor by using the data contained in the selected
message.”

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CONCLUSION
In summary, we have sustained the Examiner’s 35 U.S.C. § 103(a)
rejections of all of the claims on appeal. Therefore, the decision of the
Examiner rejecting claims 1-9, 11-19, and 21-26 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(effective
September 13, 2004).
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AFFIRMED

eld

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