Ex Parte NewportDownload PDFBoard of Patent Appeals and InterferencesJun 28, 201210961739 (B.P.A.I. Jun. 28, 2012) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte WILLIAM T. NEWPORT ____________ Appeal 2010-002149 Application 10/961,739 Technology Center 2100 ____________ Before LANCE LEONARD BARRY, ST. JOHN COURTENAY III, and JAMES R. HUGHES, Administrative Patent Judges. HUGHES, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1-3 and 17-19, which are the remaining claims in the application. Claims 4-16 and 20 were canceled during prosecution. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. Appeal 2010-002149 Application 10/961,739 2 Invention Appellant’s invention relates generally to computers. More particularly, the invention on appeal is directed to “managing shared memory in the computers.” (Spec. 1: 8-10.)1 Representative Claim Independent claim 1, reproduced below with the key disputed limitations emphasized, further illustrates the invention: 1. A method comprising: receiving a memory segment handle to an allocated memory segment in a first memory, wherein the allocated memory segment was allocated to a first logical partition by a first client that accesses the first memory via first addresses that have a size of a first number of bits; mapping the memory segment handle from the first memory into an address space of a second memory, wherein the second memory is accessed by a second client via second addresses that have a size of a second number of bits, wherein the first number of bits and the second number of bits are different; receiving a remote procedure call from the first client, wherein the remote procedure call requests a data transfer between the first memory allocated to the first logical partition and the second memory shared among a plurality of logical partitions, wherein the plurality of logical partitions execute different operating systems, and wherein the plurality of logical partitions are allocated a same processor; and 1 We refer to Appellant’s Specification (“Spec.”), Appeal Brief (“Br.”) filed March 16, 2009. We also refer to the Examiner’s Answer (“Ans.”) mailed June, 24, 2009. Appeal 2010-002149 Application 10/961,739 3 copying data between the first memory allocated to the first logical partition and the second memory shared among the plurality of logical partitions, wherein the first memory and the second memory are accessed by different applications executing in the logical partitions via the first addresses that have the first number of bits and the second addresses that have the second number of bits. Rejections on Appeal2 1. The Examiner rejects claims 1-3 and 17-19 under 35 U.S.C. § 112, first paragraph as failing to comply with the written description requirement. 2. The Examiner rejects claims 1 and 17 under 35 U.S.C. § 103(a) as being unpatentable over Glasco (US Pat. Pub. No. 2003/0225909 A1), Carter (US Patent No. 5,909,540), Tarui (US Patent No. 6,510,496 B1), and Smith (US Patent Pub. No. 2002/0124165 A1). 3. The Examiner rejects claims 2, 3, 18, and 19 under 35 U.S.C. § 103(a) as being unpatentable over Glasco, Carter, Tarui, Smith, and Morioka (US Patent No. 6,631,447 B1). ISSUES 1. Under § 112, first paragraph, did the Examiner err in finding that Appellant’s Specification failed to support that the allocated memory segment is not necessarily allocated to a first logical partition. 2. Under § 103, did the Examiner err in finding that the cited combination of references would have collectively taught or suggested: 2 Appellant’s Brief refers to objections to the claims and drawings. (Br. 12.) However, as noted by the Examiner (Ans. 3.) the objections relate to petitionable subject matter under 37 CFR 1.181 and are therefore not before us. Appeal 2010-002149 Application 10/961,739 4 a first client that accesses the first memory via first addresses that have a size of a first number of bit . . . , wherein the second memory is accessed by a second client via second addresses that have a size of a second number of bits, wherein the first number of bits and the second number of bits are different, within the meaning of independent claim 1 and the commensurate language of claim 17? ANALYSIS Rejection Under § 112, first paragraph The Examiner contends that the claimed limitation, “wherein the allocated memory was (emphasis added) allocated to a first logical partition,” is subject to two interpretations. One of the interpretations, that the allocated memory segment is not necessarily allocated to a first logical partition, is not supported in the Specification. (Ans. 3.) Appellant contends that the limitation at issue is subject to one interpretation, which is fully supported by the Specification. (Br. 18-19.) We agree for essentially the same reasons argued by Appellant. As argued by Appellant, the cited portions of the Specification describe that the allocated memory segment has already been allocated to the first partition. (Id.) Therefore, the limitation “the allocated memory segment was allocated to a first logical partition,” is fully supported by the Specification. Based on this record, we conclude that the Examiner erred in finding that the limitation “the allocated memory segment was allocated to a first logical partition,” is not supported by the Specification. Appeal 2010-002149 Application 10/961,739 5 Obviousness Rejection of Claims 1 and 17 Appellant contends that the cited combination of references fail to teach or suggest that the first memory is accessed via first addresses that have a size of a first number of bits, the second memory is accessed via second addresses that have a size of a second number of bits, wherein the first number of bits and the second number of bits are different. (Br. 20-21.) We agree for essentially the same reasons argued by Appellant. (Id.) It is our view that the cited portions of Tarui merely describe rearranging the addresses into arbitrary positions, and not accessing two memory locations, the addresses of the memory locations being of different sizes, as claimed. Based on this record, we conclude that the Examiner erred in rejecting claims 1 and 17 for essentially the same reasons argued by Appellant discussed supra. Accordingly, we reverse the Examiner’s rejection of independent claims 1 and 17. Obviousness Rejection of Claims 2, 3, 18, and 19 As noted above, dependent claims 2, 3, 18, and 19 are rejected as unpatentable over Glasco, Carter, Tarui, Smith, and Morioka. We do not find, nor has the Examiner established, that Morioka cures the deficiencies of Glasco, Carter, Tarui and Smith discussed supra. Accordingly, we reverse the Examiner’s rejection of claims 2, 3, 18, and 19 for the same reasons discussed supra. CONCLUSIONS OF LAW Appellant has shown that the Examiner erred in rejecting claims 1-3 and 17-19 under 35 U.S.C. § 112, first paragraph. Appeal 2010-002149 Application 10/961,739 6 Appellant has shown that the Examiner erred in rejecting claims 1-3 and 17-19 under 35 U.S.C. § 103. DECISION We reverse the Examiner’s rejection of claims 1-3 and 17-19 under 35 U.S.C. § 112, first paragraph. We reverse the Examiner’s rejections of claims 1-3 and 17-19 under 35 U.S.C. § 103(a). REVERSED tkl Copy with citationCopy as parenthetical citation