Ex Parte Mukund et al

Board of Patent Appeals and Interferences

May 23, 2012

10712711 (B.P.A.I. May. 23, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/712,711 11/12/2003 Shridhar Mukund ADAPP222 9276
25920 7590 05/23/2012
MARTINE PENILLA GROUP, LLP
710 LAKEWAY DRIVE
SUITE 200
SUNNYVALE, CA 94085
EXAMINER
LO, SUZANNE
ART UNIT PAPER NUMBER
2128
MAIL DATE DELIVERY MODE
05/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte SHRIDHAR MUKUND and JINESH PARIKH
____________________

Appeal 2010-002868
Application 10/712,711
Technology Center 2100
____________________

Before THOMAS S. HAHN, BRADLEY W. BAUMEISTER, and
JENNIFER S. BISK, Administrative Patent Judges.

BISK, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2010-002868
Application 10/712,711

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SUMMARY
This is an appeal under 35 U.S.C. § 134 from the Examiner’s rejection
of claims 1-19. We have jurisdiction under 35 U.S.C. § 6(b).
Claims 1-19 stand rejected under 35 U.S.C. § 103(a) as unpatentable
over Shimogori (US 2002/0152061 A1; Oct. 17, 2002) and Shridhar
(US 5,815,714; Sep. 29, 1998).
We affirm-in-part.

STATEMENT OF THE CASE
Appellants’ invention relates to “a method and apparatus for
improving the simulation and testing of a semiconductor based multi-
processor system.” Spec. 1. Claim 1, reproduced below, is illustrative of the
claimed subject matter:
1. A method for simulating a model of a chip circuit,
comprising method operations of:
defining a library of components for a processor;
defining interconnections for a set of pipelined processors
including the processor, the interconnections defined by
analyzing the architectural representation of adjacent
processors;
generating a processor circuit by combining the library of
components and the interconnections for the set of pipelined
processors;
generating a code representation of a model of the set of
pipelined processors; and
comparing signals generated by the code representation to
signals generated by the processor circuit,
wherein if the comparison of the signals is unacceptable, the
method includes,
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Application 10/712,711

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generating output for display to identify a cause of the
unacceptable comparison of the signals at a block level of the
processor circuit.
The Examiner finds that Shimogori discloses all limitations of claim 1
except “generating output for display to identify a cause of the unacceptable
comparison of the signals at a block level of the processor circuit” and
therefore relies on Shridhar for teaching “inserting a print command to
determine the signal level location of an error.” Ans. 3. The Examiner
concludes that “[i]t would have been obvious to one of ordinary skill in the
art at the time of the invention to combine the chip circuit simulation method
of Shimogori with the debugging print commands of Shridhar in order to
provide convenient means for modifying the underlying source code as
required.” Id.
Appellants assert that the combination of Shimogori and Shridhar
does not teach or suggest “block level processing and running a second
simulation with a patch applied at the block level to further identify a signal
level location of the error.” App. Br. 6.

ANALYSIS
Claims 1-5 and 9-19
First, Appellants argue that neither of the cited references teaches
block level processing as required by the claims. App. Br. 6-8. Appellants
assert that the Specification, on the other hand, “implicitly” defines “block
level” as a “high level (hardware) functional chip functional chip component
such as [a] memory block.” Reply Br. 2. According to Appellants, the
Examiner improperly equates the block level processing required by the
claims to “parts of C language source code that are converted to VU
Appeal 2010-002868
Application 10/712,711

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instructions” in Shimogori. App. Br. 6. The Examiner, however, interprets
block level processing as “representation at the device level wherein there
are blocks of code, or objects which may be converted into hardware.” Ans.
8. Both the Examiner and Appellants point to the same language in the
Specification to support their respective positions:
Another trend occurring with the semiconductor chips
being produced is that the designs are becoming more modular,
where common blocks are replicated a number of times in the
chip design. Figure 1 is a simplified block diagram of a
modular design of a semiconductor chip. Chip 100 includes
blocks A-F, where block A is represented twice. For example,
block A could be a memory that is replicated. It should be
appreciated that the replication can be exactly the same block or
substantially the same block.
Spec. 1:22–2:4. We agree that the Examiner’s definition comports with the
language in the Specification. We also agree that using this definition of
block level processing, the simulation method described in Shimogori
operates using block level processing. See, e.g., Shimogori ¶ [0096] (“[P]arts
of the specification that are converted into VUs become hardware . . . .”).
Second, Appellants argue that Shimogori does not disclose identifying
an error as required by the claims. App. Br. 7. According to Appellants,
Shimogori teaches identifying and fixing a performance delay, but the
claimed invention requires identifying an error which is “a defect in a chip
that when left undetected can cause drastic consequences during the
operation of the chip.” Id. We are not persuaded by this argument. Claim 1
does not recite the term “error.” Instead, claim 1 requires identifying “a
cause of the unacceptable comparison of the signals at a block level.” The
Specification does not define the term “unacceptable” or preclude the term
from covering a performance problem.
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Application 10/712,711

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Thus, we are not persuaded by Appellants’ arguments (App. Br. 6-8;
Reply Br. 2-4) that the combination of Shimogori and Shridhar would not
have rendered obvious independent claim 1. Accordingly, we sustain the
rejection of independent claim 1 under 35 U.S.C. § 103(a). We also sustain
the rejection of claims 2-5 and 9-19, which Appellants do not argue
separately. App. Br. 10.
Claims 6-8
Independent claim 6 reads as follows:
6. A method for debugging a processor circuit, comprising:
identifying a block level location having an error from a first
simulation;
inserting a patch into a thread specific to the block level
location of the error;
executing [a second] simulation to determine a signal level
location of the error through information generated by the
patch; and
correcting a code representation of a processor associated with
the error.
Appellants argue that independent claim 6 is patentable for the
additional reason that Shimogori does not teach or suggest “executing [a
second]1 simulation to determine a signal level location of the error through
information generated by the patch” as required by the claim. App. Br. 7-8.
The Examiner does not dispute this contention, but asserts that “the
limitation of intended use ‘to determine a signal level location of the error

1 The actual language of the disputed limitation is “executing the simulation
to determine a signal level location of the error through information
generated by the patch.” (emphasis added). Claim 6 does not recite an
antecedent basis for “the simulation.” However, since both the Examiner and
Appellants appear to interpret “the simulation” as a second simulation, this
is how we will interpret this term for purposes of this appeal.
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through information generated by the patch’” is not given patentable weight
because it simply recites the intended use and does not result in a structural
difference between the claimed invention and the prior art. Ans. 10. The
Examiner asserts that because Shimogori teaches “inserting a patch” and
“executing the simulation a second time,” it is capable of performing the
intended use and renders claim 6 obvious. Id.
We do not agree with the Examiner’s reasoning. The language “to
determine a signal level location of the error through information generated
by the patch” does not simply “define a context in which the invention
operates.” See Boehringer Ingelheim Vetmedica, Inc. v. Schering-Plough
Corp., 320 F.3d 1339, 1345 (Fed. Cir. 2003). Instead, we find that the phrase
describes the functionality of a particular step in the claimed method.
Without “determin[ing] a signal level location of the error,” when the
simulation is executed, the last step of the method, “correcting a code
representation of a processor associated with the error,” has no meaning.
We also do not agree with the Examiner’s conclusion that Shimogori
is capable of performing the “intended use.” Nothing in the portions of
Shimogori pointed to by the Examiner suggests that applying a patch to the
section of code with a performance problem and performing a second
execution of the simulation will result in the determination of an error that
can be corrected.
Accordingly, we do not sustain the rejection of independent claim 6
under 35 U.S.C. § 103(a). We likewise do not sustain the rejection of claims
7 and 8, which depend from claim 6.

Appeal 2010-002868
Application 10/712,711

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DECISION
The Examiner’s decision rejecting claims 1-5 and 9-19 is affirmed.
The Examiner’s decision rejecting claims 6-8 is reversed.

AFFIRMED-IN-PART

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