Ex Parte Moyer et al

Board of Patent Appeals and Interferences

Jun 26, 2012

11278725 (B.P.A.I. Jun. 26, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte WILLIAM C. MOYER, IMRAN AHMED, and DAN TAMIR
____________________

Appeal 2009-010279
Application 11/278,725
Technology Center 2100
____________________

Before LANCE LEONARD BARRY, ST. JOHN COURTENAY III, and
THU A. DANG, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

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I. STATEMENT OF THE CASE
Appellants appeal from the Examiner’s final rejection of claims 19-21
under 35 U.S.C. § 134(a) (2007). We have jurisdiction under 35 U.S.C.
§ 6(b) (2007).
We reverse.

A. INVENTION
According to Appellants, the invention relates in general to data
processing and more specifically to a data processing system having bit
exact instructions and methods therefor (Spec. 1, ¶ [0001]).

B. ILLUSTRATIVE CLAIM
Claim 19 is exemplary and is reproduced below:
19. A data processing system, comprising:

means for storing a first portion of an instruction,
wherein the first portion of the instruction selects a vector
operation;

means for storing a second portion of the instruction,
wherein the second portion of the instruction selects operand
width used in the vector operation;

means for storing a third portion of the instruction,
wherein the third portion of the instruction selects one of an
addition operation and a subtraction operation to be used in the
vector operation;

means for storing a fourth portion of the instruction,
wherein the fourth portion of the instruction selects signed or
unsigned for the vector operation;
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means for storing a fifth portion of the instruction,
wherein the fifth portion of the instruction selects saturated or
unsaturated for the vector operation;

means for storing a sixth portion of the instruction,
wherein the sixth portion of the instruction selects fractional or
integer for the vector operation;

means for storing a seventh portion of the instruction,
wherein the seventh portion of the instruction selects one or
more of an upper portion of a destination register and a lower
portion of the destination register for storing a bit exact result of
the vector operation;

means for storing an eighth portion of the instruction,
wherein the eighth portion of the instruction selects a width of
the bit exact result of the vector operation; and

means for storing a ninth portion of the instruction,
wherein the ninth portion of the instruction selects a whether
the bit exact result is stored in an accumulator as well as in the
destination register.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Peleg US 5,721,892 Feb. 24, 1998
Nguyen US 6,058,465 May 02, 2000
Liao US 2002/0026569 Al Feb. 28, 2002

Claims 19 and 20 stand rejected under 35 U.S.C. § 102(b) over
Nguyen.
Claim 21 stands rejected under 35 U.S.C. § 103(a) over Peleg in view
of Liao.

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II. ISSUE
Has the Examiner erred in finding that Nguyen teaches means for
storing first through ninth portions of “an instruction” wherein the first
through fourth and sixth through ninth portions respectively select vector
operation, operand width, additional operation and subtraction, and the like,
and “the fifth portion of the instruction selects saturated or unsaturated for
the vector operation” (claim 19, emphasis added)? In particular, the issue
turns on whether Nguyen discloses that the same instruction that comprises
portions for selecting vector operations, operand width and the like also
comprises a portion that selects saturated or unsaturated for vector operation.

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Nguyen
1. Nguyen discloses a vector processor architecture in which the type
and size for data elements are defined by instructions which
manipulate operands associated with the vector register (Abstract;
Appendix E).
2. A vector control and status register VCSR is provided which
comprises an integer saturation ISAT bit which specifies saturation or
no saturation (col. 27, l. 63 to col. 28, l. 8).

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IV. ANALYSIS
Claims 19-20
Appellants contend that, with respect to Nguyen, “the Examiner first
points to an instruction containing the opcode field as the ‘instruction’ and
then points to a special purpose register, the Vector Control and Status
Register (VSCR) as the ‘instruction’” (App. Br. 9). Thus, Appellants assert
that Nguyen differs from the claimed invention of claim 19 which requires
that “the portion of the same instruction select saturated and unsaturated
operation that also has eight other portions that are used for other purposes”
(App. Br. 12).
After reviewing the record on appeal, we agree with Appellants. That
is, we cannot find any suggestion of a “fifth portion of the instruction,” the
same instruction that includes 8 other portions, which “selects saturated or
unsaturated for the vector operation,” as required by claim 19, in the sections
of Nguyen referenced by the Examiner.
In particular, the sections in Nguyen referenced by the Examiner
disclose instructions which define the type and size for data elements (FF 1)
but are silent as to any selection of saturated or unsaturated for vector
operations. Though Nguyen also discloses a VCSR register which
comprises an integer saturation bit that specifies saturation/ no saturation
(FF 2), there is no teaching in the sections of Nguyen that disclose that the
instructions include selection of saturation/no saturation. That is, there is no
teaching in the cited section of Nguyen that discloses that the same
instruction that comprises portions for selecting vector operations, operand
width and the like also comprises a portion that selects saturated or
unsaturated.
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As such, we find that the Examiner erred in rejecting claim 19 and
claim 20 depending therefrom over Nguyen.
Furthermore, Appellants point out that claim 20 also requires that “if
the bit exact result needs to be stored in both the accumulator as well as the
destination register then that can be done” (App. Br. 13). Reviewing the
records on appeal, we find no teaching of “if the ninth portion of the
instruction selects that the bit exact result is to be stored in an accumulator
as well as in the destination register, then the seventh portion of the
instruction also selects” as required by claim 20 (emphasis added) in the
portions of Nguyen referenced by the Examiner.
Though the Examiner finds that “[t]he claim only requires that the
seventh portion of the instruction select” (Ans. 10), we find no teaching of
the seventh portion selection “if the ninth portion of the instruction selects”
(claim 20), since the relied upon section of Nguyen does not disclose such
conditional nature.
Claim 21
As for claim 21, Appellants contend that “[a]t best, Peleg teaches
saturating the result of an operation, if the result overflows or underflows”
(App. Br. 15) and that “pursuant to Liao any saturation will be done as part
of the load/store” (App. Br. 16). Thus, according to Appellants, the
references combined “would result in the saturation being performed twice”
(id.). Accordingly, Appellants contend that the references do not disclose or
suggest “saturating the first intermediate product, if the first intermediate
product overflowed or underflowed, concurrently saturating the second
intermediate product, if the second intermediate product overflowed or
underflowed and concurrently saturating the third intermediate product, if
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the third intermediate product overflowed or underflowed” as required by
claim 21 (App. Br. 15).
After reviewing the record on appeal, we agree with Appellants. That
is, we cannot find any suggestion of saturating a first intermediate product if
the first intermediate product overflowed or underflowed and concurrently
saturating the second or third intermediate product, if the second or third
intermediate product overflowed or underflowed, as required by claim 21, in
the sections of Peleg and Liao referenced by the Examiner.
As such, we find that the Examiner erred in rejecting representative
claim 21over Peleg in view of Liao.

V. CONCLUSION AND DECISION
We reverse the Examiner’s rejection of claims 19 and 20 under 35
U.S.C. § 102(b) and of claim 21 under 35 U.S.C. § 103(a).

REVERSED

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