Ex Parte Moon et al

Patent Trial and Appeal Board

Jun 29, 2018

14512885 (P.T.A.B. Jun. 29, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/512,885 10/13/2014 Young-Suk Moon
96767 7590 07/03/2018
William Park & Associates LTD.
930 N. York Road, Suite 201
Hinsdale, IL 60521
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
PA1852-0 1461
EXAMINER
THOMAS, JAMES JORDAN
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
07 /03/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspto.actions@wpapat.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YOUNG-SUK MOON and HONG-SIKKIM
Appeal 2017-011746
Application 14/512,885 1
Technology Center 2100
Before BARBARA A. BENOIT, JASON J. CHUNG, and PHILLIP A.
BENNETT, Administrative Patent Judges.
BENNETT, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's final
rejection of claims 1-17. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
1 Appellants' Brief ("App. Br.") identifies SK hynix Inc. as the real party in
interest. App. Br. 2.
Appeal 2017-011746
Application 14/512,885
CLAIMED SUBJECT MATTER
The claims are directed to a semiconductor device, which employs a
wear leveling operation to prevent deterioration of memory cells caused by
concentrated accesses. Spec. i-f2. Claim 1, reproduced below with the key
limitation in italics, is illustrative of the claimed subject matter:
1. A semiconductor device comprising:
a first address cache configured to store a physical
address of a semiconductor memory device and a write count
associated with the physical address;
an address monitor configured to update the physical
address and the write count in the first address cache based on a
received write request; and
an arbiter configured to store a write address and write
data associated with the write request in a write cache in response
to a command from the address monitor, wherein the command
generated by the address monitor is based on the physical address
and the write count in first address cache, wherein the write cache
stores data corresponding to a physical address being mapped to
a logical address when the physical address being accessed by
write requests more than a threshold value before the physical
address is remapped to another logical address.
App. Br. 15 (Claims Appendix).
REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Woodman
Shanmuganathan
Bell
MIURA
Koka
Dong
us 5,996,055
US 2008/0162786 Al
US 2012/0151141 Al
US 2012/0265925 Al
US 2014/0052917 Al
US 2014/0237160 Al
2
Nov. 30, 1999
Jul. 3, 2008
Jun. 14,2012
Oct.18,2012
Feb.20,2014
Aug. 21, 2014
Appeal 2017-011746
Application 14/512,885
REJECTIONS
Claims 1, 2, 5-7, and 11 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Woodman, Shanmuganathan, and Bell. Final Act.
3-10.
Claims 3 and 4 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Woodman, Shanmuganathan, Bell, and Koka. Final Act.
8-10.
Claims 8 and 9 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Woodman, Bell, Shanmuganathan, and Dong. Final Act.
10-11.
Claim 10 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Woodman, Shanmuganathan, Bell, and Miura. Final Act.
11-12.
Claims 12, 13, and 15 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Woodman and Bell. Final Act. 13-15.
Claim 14 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Woodman, Bell, and Koka. Final Act. 15-17.
Claims 16 and 17 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Woodman, Bell, and Dong. Final Act. 17-18.
ISSUE
Has the Examiner erred in finding Woodman teaches or suggests "a
first address cache configured to store a physical address of a semiconductor
memory device and a write count associated with the physical address," as
recited in claims 1 and 11, and similarly in claim 12?
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Application 14/512,885
ANALYSIS
Claim 1 recites the limitation "a first address cache configured to store
a physical address of a semiconductor memory device and a write count
associated with the physical address." In rejecting claim 1, the Examiner
finds Woodman's translation buffer 17 teaches "a first address cache" and
that the first address cache is "configured to store a physical address of a
semiconductor memory device." Ans. 2-3 (citing Woodman Fig. 1, col. 3,
1. 57---col. 4, 1. 2; col. 4, 11. 16-30). The Examiner acknowledges "Woodman
does not explicitly disclose a (first) address cache configured to store a write
count associated with the physical address." Ans. 3. The Examiner finds
Woodman nevertheless renders this limitation obvious because it teaches the
use of cache page address activity counters. Ans. 5. The Examiner finds the
"cache page address activity counters are write counts [because] the counters
track the activity of a virtual address, [which in tum has] a related or
associated physical address." Ans. 4 (citing Woodman col. 21, 11. 19-31 ).
The Examiner concludes it would have been obvious to store the counter
information because it "would allow for quicker access time[ s] and faster
processes." Id. at 5.
Appellants argue Woodman is insufficient to render the limitation
obvious because the cache page activity counters are not part of the address
cache, but instead are "included in the page allocator, which is included in
the memory device separate from the TB [translation buffer] 17 included in
CPU subsystem." Reply Br. 6 (citing Woodman Fig. 15, col. 20, 11. 26-30);
see Woodman col. 3, 11. 46-50 (indicating Fig. 15 is an embodiment of a
memory controller for monitoring the activity of pages and performing
virtual-to-physical remapping when a cache page address is incurring excess
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Application 14/512,885
activity). Appellants further argue activity count relied upon by the
Examiner is not a "write count" because its value changes based on any
command issues, regardless of whether it is a "write" command. Reply Br.
7. Appellants further argue a person of ordinary skill in the art "would not
be inclined to relocate the activity counter disposed in the process counter to
the translation buffer since the activity counter clearly requires the index
derived from process and cache page address information." Reply Br. 7.
We agree with Appellants.
The disputed limitation recites an address cache configured to store
two items of information: (1) a physical address of semiconductor memory
device; and (2) a write count associated with that same physical memory
address. The Examiner finds Woodman's translation buffer 17 stores a
physical memory address, but acknowledges that it does not store a write
count associated with that address. Instead, the Examiner concludes it
would have been obvious to modify Woodman such that the translation
buffer also stores a cache page address activity count. .
We are persuaded by Appellants that the proposed modification would
not have been obvious to a person of ordinary skill in the art. The
modifications to Woodman needed to meet the disputed limitation are two-
fold. First, the activity counter would need to be moved from its location
within Woodman's memory controller to the CPU subsystem, which houses
the translation buffer (so that the activity counter is stored by the recited
"first address cache" as required by claim 1 ). Second, the operation of the
counter would need to be modified to change the counter from a general
activity counter to a more specific write counter (so that a "write count" is
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Application 14/512,885
generated). The Examiner has not explained sufficiently why a skilled
artisan would have been prompted to make these significant changes.
With respect to the first modification, the Examiner finds a person of
skill in the art would have repositioned the activity counters "since having
the write count in the address cache would allow for quicker access time and
faster processes." Ans. 5. However, as Appellants persuasively argue, the
activity counter is disposed within the process counter 360 and is intended to
"indicate[] the relative activity of a cache page address within a given
process" and does so by using an index within the process counter 360 "to
access the appropriate activity counter ... to allow the activity counter to be
incremented." Reply Br. 6-7, emphasis omitted (quoting Woodman col. 21,
11. 15-18). Moving the activity counters out of the process counter 360 and
away from the index would impede access to the activity counter, and make
it more difficult for the index to access the activity counter to allow it to be
incremented. In finding that moving the activity counters from a memory
controller to the CPU system would be motivated by quicker access time and
faster processes, the Examiner does not address this trade-off sufficiently.
Thus, we conclude that the Examiner's reasoning is insufficient to support
the finding that an ordinarily skilled artisan would have been motivated to
reposition the activity counters to the translation buffers in the CPU
subsystem.
We also agree with Appellants that the Examiner has not explained
sufficiently why an ordinarily skilled artisan would have been motivated to
make the second necessary modification---changing the counter from an
activity count to a write count. The Examiner finds that in situations where
only write operations take place, Woodman's activity counter effectively
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operates as a write counter. But the Examiner identifies no teachings in
Woodman that indicate such a situation is likely, or even possible.
Moreover, we discern no benefit that would be achieved by such a
modification. After all, the purpose of maintaining the activity count in
Woodman is to identify excessive thrashing in a virtual address mapping.
See Woodman col. 21, 11. 19--31. Limiting the count to write operations
would not further that purpose.
In sum, we agree with Appellants that neither Woodman nor the
remaining cited references teach or suggest a semiconductor device that
includes the an address cache configured to store a physical memory address
and a write count associated with the stored physical memory address, as
required by claim 1. Accordingly, we are persuaded the Examiner has erred
in rejecting claim 1, and we do not sustain its rejection.
Independent claim 11 was rejected under the same reasoning as claim
1. Final Act. 3 ("As to claims 1 & 11, Woodman discloses ... "). Although
claim 11 differs from claim 1 in that it recites a "semiconductor memory
device" and a "controller configured to control the semiconductor memory
device," we agree that the reasoning above also applies to claim 11. In
rejecting claim 11, the Examiner finds memory 18, which includes cache
page address activity counters, corresponds to the recited "semiconductor
memory device" and CPU subsystem 12, which includes translation buffer
1 7, corresponds to the recited "controller configured to control the
semiconductor memory device." Thus, based upon these findings, the same
modifications to Woodman would be necessary to achieve the configuration
of claim 11. Because we agree with Appellants that those modifications
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would not have been obvious, we also do not sustain the rejection of claim
1 1.
Independent claim 12 recites "an operating method of a
semiconductor device," and includes the limitation "performing the write
request on a write cache when a write count associated with the write
address stored in the first address cache exceeds a threshold value." App.
Br. 18 (Claims Appendix). The specific ground of rejection for claim 12
differs from that of claims 1 and 11, however, like those claims, the rejection
of claim 12 is based primarily on Woodman. In particular, the Examiner
finds Woodman teaches "performing the write request on a cache when a
write count associated with the write address stored in the first address cache
exceeds a threshold value," explaining that "accessing the cache 16 is write
to the write cache and the write may cause the activity counter, or write
count, to exceed a threshold." Final Act. 13 (emphasis added). Appellants
argue the rejection of claim 12 is erroneous for the same reasons as claim 1.
App. Br. 15 ("claim 12 is distinguished ... based on the same reasons as ...
claim 1 "), and the Examiner expresses no disagreement with this argument.
See generally, Ans. 6-12. We agree with Appellant that the error made by
the Examiner with respect to claim 1 applies equally here. In particular,
claim 12 requires writing to a write cache "when a write count ... exceeds a
threshold value." As we explained above, Woodman does not teach the
recited "write count," and the Examiner has not explained sufficiently why a
person of ordinary skill in the art would have been motivated to change
Woodman's activity counter to operate as a write counter. Accordingly, we
also do not sustain the rejection of independent claim 12.
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The remaining claims depend from one of the independent claims
discussed above. As such, we also do not sustain their rejections for the
same reasons.
DECISION
We reverse the Examiner's rejections of claims 1-1 7.
REVERSED
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