Ex Parte Ma et al

Patent Trial and Appeal Board

Jan 9, 2013

11525982 (P.T.A.B. Jan. 9, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/525,982 09/22/2006 Qing Ma 42P6623CD2 1332
45209 7590 01/09/2013
Mission/BSTZ
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
1279 Oakmead Parkway
Sunnyvale, CA 94085-4040
EXAMINER
KARIMY, TIMOR
ART UNIT PAPER NUMBER
2894
MAIL DATE DELIVERY MODE
01/09/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte QING MA, JIN LEE, HARRY FUJIMOTO, CHANGHONG DAI,
SHIUH-WUU LEE, TRAVIS EILES, and KRISHNA SESHAN
____________

Appeal 2010-009986
Application 11/525,982
Technology Center 2800
____________

Before CARL W. WHITEHEAD, JR., ERIC S. FRAHM and ANDREW J.
DILLON, Administrative Patent Judges.

WHITEHEAD, JR., Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-009986
Application 11/525,982

2
STATEMENT OF THE CASE
Appellants are appealing claims 161, 164, 165 and 168. Appeal Brief
3. We have jurisdiction under 35 U.S.C. § 6(b) (2012).
We affirm.

Introduction
The invention is directed to integrated circuit device having a
semiconductor die attached to a carrier substrate wherein the carrier
substrate causes stress on the semiconductor die. Appeal Brief 4.

Illustrative Claim
161. An integrated circuit comprising:

a semiconductor die having a back surface attached to a carrier
substrate, wherein said carrier substrate causes a stress on said
semiconductor die;

an active area formed in said semiconductor die and comprising
nMOS device components including an n-type source region, an n-type drain
region, and a gate structure disposed adjacent to said active area between
said n-type source region and said n-type drain region; and

an isolation structure formed in said semiconductor die in the same
plane as said active area and surrounding said active area, wherein said
isolation structure comprises a trench having a material with a modulus less
than approximately 70 GPa disposed therein, and wherein said material is
configured to lessen the effect of a detrimental compressive stress on said
active region.

Appeal 2010-009986
Application 11/525,982

3
Rejection on Appeal
Claims 161, 164, 165 and 168 stand rejected under 35 U.S.C. §103(a)
as being unpatentable over Yu (U.S. Patent Number 6,010,948; issued
January 4, 2000), Vinciarelli (U.S. Patent Number 5,906,310; issued May
25, 1999) and Jain (U.S. Patent Number 5,332,868; issued July 26,
1994). Answer 3-6.

Issue on Appeal
Do Yu, Vinciarelli and Jain, either alone or in combination, disclose
“an active region having a detrimental compressive stress” and “an isolation
trench having a material configured to lessen the effect of a detrimental
compressive stress on such an active region” as claimed by Appellants? See
Appeal Brief 6.

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We disagree with Appellants’
conclusions. We concur with the findings and reasons set forth by the
Examiner in the action from which this appeal is taken and the reasons set
forth by the Examiner in the Answer in response to Appellants’ Appeal
Brief. However, we highlight and address specific findings and arguments
for emphasis as follows.
Appellants concede that Yu discloses a shallow trench isolation
method that utilizes a BPSG trench fill however it is Appellants’ contention
that Yu does not disclose an active region having a detrimental compressive
stress and also fails to disclose an isolation trench having a material
Appeal 2010-009986
Application 11/525,982

4
configured to lessen the effect of a detrimental compressive stress on such
an active region. Appeal Brief 6.
Appellants argue that Vinciarelli only discloses an assembly having a
detrimental tensile stress but not a detrimental compressive stress as required
in claim 161. Id.
However, the Examiner finds that:

[The] Yu patent teaches a trench isolation structure 4 (see
Fig. 8), wherein BPSG material is used as the trench-filler
material. Examiner notes that BPSG is one of the
commonly known material having a relatively low
modulus of elasticity, and Jain discloses an insulation or
isolation layer comprising material a with low modulus of
elasticity that is less than approximately 70 GPa. Jain
discloses polyimide in lines 16-26 and siloxane spin-on-
glass (lines 30-31) borosilicate glass (BSG) in line 56 as
the insulating material having low modulus of elasticity
less than 70 GPa, particularly Polyimide, wherein a low
modulus of 5 GPa is expressly taught (lines 25-26). Yu
discloses the structural limitations of the claims, and Jain
further provides evidence and teaching of insulating
material meeting the claimed dimension of low modulus
of elasticity, i.e. less than approximately 70 GPa.
Answer 6.
We agree with the Examiner’s findings. Appellants employ a “trench
filled with a silicon dioxide with a modus of between about 70 and 80 GPa,
as commonly used as a dielectric material in the industry.” Specification 8.
Appellants do not challenge Examiner’s assessment that BPSG is a low-
modulus dielectric material and it is evident from Appellants’ specification
that low-modulus dielectrics lessen the impact of tensile stress that occurs on
a semiconductor die and therefore Yu’s BPSG material lessens the impact of
Appeal 2010-009986
Application 11/525,982

5
tensile stress because of its low-modulus of elasticity. See Specification 10.
Furthermore, claim 161 broadly positions the isolation structure within the
same plane of the active area and Yu discloses an isolation structure
arguably within the same plane of an active area. Yu, Figure 8.
We do not find Appellants’ argument that Vinciarelli discloses
tolerable tensile and compressive stresses and therefore fail to address the
alleged deficiency of Yu to be persuasive. Appeal Brief 6. First, the
Examiner only uses Vinciarelli as evidence that stress can occur on a
ceramic substrate which a semiconductor die is mounted and second,
regardless of the tolerability of the stress, the stress still is apparent and not
easily dismissed. Answer 7. Regardless, it is Yu that discloses the structural
limitations of the invention as claimed. Id. at 3-5.
Therefore we sustain Examiner’s rejection of claim 161, as well as,
claims 164, 165 and 168 not separately argued.

DECISION
The rejection of claims 161, 164, 165 and 168 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37
C.F.R. § 41.50(f).

AFFIRMED

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