Ex Parte Lyon

Patent Trial and Appeal Board

Mar 29, 2013

11106006 (P.T.A.B. Mar. 29, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/106,006 04/14/2005 Terry L. Lyon ROC920040359US1 3621
7590 04/01/2013
Robert R. Williams
Patent Agent
IBM Corporation, Dept. 917
3605 Highway 52 North
Rochester, MN 55901-7829
EXAMINER
BERTRAM, RYAN
ART UNIT PAPER NUMBER
2187
MAIL DATE DELIVERY MODE
04/01/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte TERRY L. LYON1
____________

Appeal 2010-006776
Application 11/106,006
Technology Center 2100
____________

Before JAMESON LEE, JEREMY J. CURCURI, and JAMES B. ARPIN,
Administrative Patent Judges.

ARPIN, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1, 3-22, 24, and 25. Claims 2 and 23 are cancelled. Br.
2.2 We have jurisdiction under 35 U.S.C. § 6(b). We reverse.

1 International Business Machines, Inc. is the real party in interest.
2 Throughout this opinion, we refer to (1) the Appeal Brief (Br.) filed
September 8, 2009; and (2) the Examiner’s Answer (Ans.) mailed January
19, 2010.
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INVENTION
Appellant’s invention relates to apparatus and methods in computer
systems allowing software applications to specify an intended stride when
writing data elements into a memory. See generally Abstract. The memory
system uses a hashing mechanism that uses the intended stride to store the
data elements in such a way that accessing the data elements at the intended
stride ensures that consecutive accesses (i.e., reading or writing) are not to
the same group or bank of memory. Id. Sequential accesses of the data
elements also are not directed to the same group or bank of memory. Id.; see
also Spec. ¶ [0037]. Data elements then may be accessed without
reordering. See Spec. ¶ [0012]. Claim 1 is illustrative and is reproduced
below with a disputed limitation emphasized:
1. A computer system comprising:
a processor;
a memory control coupled to the processor;
a memory coupled to the memory control, the memory further
comprising one or more groups, each group further comprising one or
more banks;
a first memory portion resident in the memory; and
an application executing in the processor;
wherein the application provides the memory control with
information, prior to writing a first data element in the first memory
portion, about the first memory portion in the memory, including an
intended stride for data elements in the first memory portion, the
memory control using the intended stride when writing the data
elements at a first stride, the first stride not the same as the intended
stride, to distribute the data elements among the one or more groups
and the one or more banks in the one or more groups in the first
memory portion in such a way that a subsequent strided access at the
intended stride does not consecutively access a particular bank in a
particular group; and wherein the first memory portion comprises
more than one data element; and wherein a subsequent access, at the
first stride, of the data elements written to the first memory portion
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does not consecutively access a particular bank in a particular group;
and wherein reordering of accesses is not performed.

The Examiner relies on the following as evidence of unpatentability:
Barowski
Fields
Heap
US 2002/0023204 A1
US 6,493,814 B2
US 2004/0093457 A1
Feb. 21, 2002
Dec. 10, 2002
May 13, 2004
Tanenbaum, STRUCTURED COMPUTER ORGANIZATION 10-12 (2d ed. 1984).
THE REJECTION
The Examiner rejected claims 1, 3-22, 24, and 25 under 35 U.S.C.
§ 103(a) as unpatentable over Fields, Barowski, Tanenbaum, and Heap.
Ans. 3-16.

OBVIOUSNESS REJECTION OVER FIELDS, BAROWSKI,
TANENBAUM, AND HEAP
Regarding illustrative claim 1, the Examiner finds that Fields teaches
all of the limitations of claim 1, except for “an application executing in the
processor” and the recited functions performed or not performed by that
application, including that “reordering of accesses is not performed.” Ans.
3-5 (citing Fields, col. 1, ll. 58-60; col. 2, l. 43-col. 3, l. 30; Fig. 1).
Nevertheless, the Examiner finds that Barowski teaches “stride predicted
memory accesses, wherein a data structure contains a predicted stride for
each hashed memory address[, wherein] [t]his stride may be used to fetch a
next predicted word from memory.” Id. at 5 (citing Barowski, ¶¶ [0007]-
[0015]; Figs. 2, 4). Although Barowski teaches a “hardware–provided
intended stride for a memory portion” (emphasis added), the Examiner finds
that Tanenbaum teaches that software (e.g., an application) is logically
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equivalent to hardware. Id. (citing Tanenbaum, 11). Further, the Examiner
finds that “Heap teaches that a stride pattern may be set before [the] writing
[of] data [to memory portion]” and the use of multiple strides, each of which
avoids consecutive bank access conflicts. Id. (citing Heap, ¶¶ [0010],
[0013], [0040]; Figs. 5A-C).
Appellant argues that neither Barowski nor Tanenbaum, alone or in
combination, teaches that information, including an intended stride, shall be
used for future access to the memory portion. Br. 7-8. Moreover, Appellant
argues that Heap does not teach writing data at an intended stride to achieve
increased bandwidth or avoiding reordering of accesses. Id. at 8-9.
ISSUE
Under § 103, has the Examiner erred in rejecting claim 1 by finding
that Fields, Barowski, Tanenbaum, and Heap, collectively, teach or suggest
that “reordering of accesses is not performed”?3
ANALYSIS
We begin by construing the disputed limitation of claim 1 which calls
for, in pertinent part, that “reordering of accesses is not performed.” As
Appellant notes, “[m]athematical operations are subsequently performed on
the data in the mathematical matrix, often not in the same order that the data
was written into the mathematical matrix.” Spec. ¶ [0006] (“Description of
the Related Art”; emphasis added); see also Spec. ¶ [0001] (describing
writing data to memory in a first order and reading data in a second order).
We apply to the language of the claim “the broadest reasonable meaning of

3 Although Appellant contests other aspects to the Examiner’s rejection of
claim 1, we find this issue, regarding whether the combined references
teach, and, in particular, whether Heap teaches that “reordering of accesses
is not performed,” is dispositive.
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the words in their ordinary usage as they would be understood by one of
ordinary skill in the art, taking into account whatever enlightenment by way
of definitions or otherwise that may be afforded by the written description
contained in the applicant's specification.” In re Morse, 127 F.3d 1048,
1054 (Fed. Cir. 1997) (emphasis added). Although Appellant does not
define the term “reordering,” we find that Heap provides a pertinent
description of “reordering.” In particular, Heap states that reordering is a
method of accomplishing interleaving,4 “such that different banks are used
for consecutive accesses. A plurality of memory accesses are queued or
buffered in [a memory controller]. The accesses are then issued from the
buffer in a different order, so that different banks are used for consecutive
memory accesses.” Heap, ¶ [0009] (emphasis added).
Referring to Figure 5C, Heap’s reorder buffer 1002 operates, such that
“data may be written with a stride of 1 without consecutively accessing a
particular bank.” Amendment 7 (Dec. 2, 2008; citing Heap, ¶ [0040]). In
Figure 5C, Heap depicts the reordering of Bank Addresses across Banks in
order to avoid consecutive accessing. Compare Heap, Fig. 5C (Bank
Address 1 containing Banks 6, 4, 5, 7) with Heap, Fig. 1B (Bank Address 1
containing Banks 4, 5, 6, 7); see also Heap, Fig. 4C (similar reordering to
that depicted in Fig. 5C). As a result of the Examiner’s reliance upon Heap
in combination with Fields, Barowski, and Tananbaum, Appellant amended

4 A pertinent definition of the term “interleaved memory” is “[a] method of
organizing the addresses in RAM memory in order to reduce wait states.
In interleaved memory, adjacent locations are stored in different rows of
chips so that after accessing a byte, the processor does not have to wait an
entire memory cycle before accessing the next byte.” MICROSOFT COMPUTER
DICTIONARY 280 (5th ed. 2002).
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claim 1 (and claim 22) to proscribe “reordering” of the memory accesses.
Amendment 2 (claim 1), 4-5 (claim 22). Consequently, we construe
Appellant’s claim 1 to require that the accessing of the first data element is
not reordered and that the first data element is accessed in the same order in
which it is written to the memory.
Based on the record before us, we find that the Examiner erred in
rejecting claim 1 which calls for, in pertinent part, that “reordering of
accesses is not performed.” Heap is directed to systems and methods for
mapping addresses to memory banks that reduces conflicts and increases
bandwidth.5 Heap, ¶ [0001]. Further, Heap describes that, in order to obtain
maximum system performance, a data bus needs to be kept busy and that
one way to accomplish this is to interleave consecutive memory accesses to
different banks. Id. at [0005]. In particular, Heap describes three ways to
accomplish such interleaving: first, by reordering the memory accesses (id.
at [0009]); second, by interleaving across low-order bits of the address
request (id. at [0010]); and, third, by using a prime number of banks with
each bank having 2x rows and columns (id. at [0011] (interleaving relies on
mapping addresses to banks by calculating address mod banks).
Referring to Heap’s Paragraph [0010], the Examiner contends that
Heap describes that particularly selected strides may be used to avoid
interleaving. Ans. 5; Final Rej. 4. Although the Examiner is correct, Heap
explains that “this manner [of interleaving] works well for random
addresses or addresses with strides of 1.” Heap, ¶ [0010] (emphasis added).

5 The Examiner finds that Heap’s banks 0-3 correspond to Appellant’s
recited “groups,” and Heap’s memory or bank addresses correspond to
Appellant’s recited “banks.” See Ans. 14.
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Because the use of “random addresses” implies accessing non-sequentially
ordered addresses and because, according to claim 1, Appellant’s “first
stride [is] not the same as the intended stride;” neither of these conditions
comports with Appellant’s system, as recited in claim 1.
In support of the obviousness rejection of claim 1, the “Examiner
considers the unmodified memory layout of Heap’s admitted prior art Figure
1B and paragraph 40 which describes a memory having 32 addresses divided
across 4 banks.” Ans. 19. Nevertheless, we determine that the Examiner
improperly combines Heap’s teaching regarding the particular embodiment
of the prior art depicted in Figure 1B, with Heap’s teaching regarding an
embodiment of the disclosed system of Heap’s Paragraph [0040] and
Figures 5A-C. In particular, referring to Paragraph [0006], Heap explains
that “Fig. 1B depicts an example 150 of a prior art address mapping to the 4
bank memory of Fig. 1A. . . . In this manner, consecutively addressed
transactions, that is addresses with stride 1, will be mapped to different
banks” (emphasis added).
The Examiner contends that, if a stride of 3 is applied to the memory
of Heap’s Figure 1B, which is addressed with stride 1, the use of stride 3
would not consecutively access banks in Figure 1B. Ans. 19. From Heap’s
Figure 1B, the Examiner “extrapolates that any stride which is not a multiple
of the number of the banks . . . will not consecutively access a bank.” Id.
Nevertheless, with respect to Heap’s Figure 1B, Heap describes writing the
data to and reading the data from the memory at the same stride, i.e., a stride
of 1. Heap, ¶¶ [0006], [0010]. The Examiner does not demonstrate,
however, where Heap teaches the writing of data to memory at an intended
stride, such as a stride of 1, and the accessing of that data at a first stride,
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such as a stride of 3; nor does the Examiner demonstrate that Heap’s Figure
1B would be the same if written at a different stride.
In recognition of this deficiency in Heap, the Examiner states that
“[p]erhaps the question remains whether Barowski may provide a stride of 1
or 3. Indeed, in the simplest case [sic] is just to use a constant value
(Barowski, paragraph 11)” (emphasis added). Ans. 19-20. Nevertheless, in
Paragraph [0011], Barowski describes determining a predicted value based
on a last value or a last value increased by a certain stride. Specifically,
Barowski describes that “[a] stride predictor uses a pattern of one constant
stride. And a certain pattern of values is modelled by recording the pattern
of deltas between the values and adding the deltas to the last value.” Br. 8
(quoting Barowski, Abstract (emphases in original)). Thus, Barowski
discloses a predicted stride derived from a pattern of values; and, to the
extent that the Examiner suggests that Appellant recites the use of a
“constant” stride, e.g., that an intended stride and a first stride are the same,
that suggestion would be contrary to the plain language of claim 1. Id. at 8-
9.
Referring to Heap’s Paragraph [0040], the Examiner contends that
Heap teaches that “in another embodiment address remapping can be used
such that more arbitrary strides may be used.” Ans. 5; Final Rej. 4.
Although, in Paragraph [0040], Heap describes the use of other stride values,
we find that this use of other stride values occurs in the context of Heap’s
Figures 5A-C, which determine the bandwidth for strides 1-4. In particular,
referring to Figure 5C, Heap depicts a memory with reordered bank
addresses. Heap, ¶ [0040] (“since stride 3 uses all four banks with
reordering”; emphasis added); see Br. 9-10. The Examiner acknowledges
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that the overall disclosure of Heap teaches the reordering of memory
accesses. Ans. 20. Moreover, the Examiner acknowledges that, in Figure
10, Heap teaches reordering of memory accesses, preferably, by means of
reorder buffer 1002; but the Examiner contends that Figure 10 is not relied
upon in that rejection of claim 1. Id. In addition, referring to Figures 4A-C
and 5A-C, the Examiner contends that “[t]he reordering is non-essential for
the address remapping of Heap.” Final Rej. 16. We disagree.
With respect to the embodiment of Heap’s system depicted in Figures
4A-C, we note that Heap states that “re-ordering is necessary to reduce the
chance of random consecutive accesses from going to the same bank.”
Heap, ¶ [0034] (emphasis added). Further, as discussed above, we find that
Heap describes reordering in Paragraph [0040] which describes Figures 5A-
C and depicts reordered addresses in Figure 5C. Thus, we are not persuaded
that reordering is not essential for Heap’s remapping of addresses.
Moreover, the Examiner states that the disputed limitation “has not been
addressed any more specifically because it is a negative limitation which is
performed by neither the claimed invention nor the prior art (as applied).”
Ans. 20. The use of a negative limitation to define the limits of the claimed
subject matter is permissible. In re Wakefield, 422 F.2d 897, 904 (CCPA
1970). As recited in claim 1, Appellant’s system does not perform
reordering of memory accesses, but, for the reasons set forth above, we are
not persuaded that Heap, as applied, does not teach or suggest the proscribed
reordering. Therefore, the Examiner fails to demonstrate that the proposed
combination of references teaches or suggests all of the limitations of
Appellant’s system, as recited in claim 1, including “wherein reordering of
accesses is not performed.”
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For the foregoing reasons, Appellant has persuaded us of error in the
rejection of: (1) independent claim 1; (2) independent claim 22, which
recites “subsequently accessing data elements at [an] intended stride . . . with
no reordering of accesses being performed” (emphasis added); and (3)
dependent claims 3-21, 24, and 25, which are not argued separately with
particularity.

CONCLUSION
The Examiner erred in rejecting claims 1, 3-22, 24, and 25 under
§ 103(a).

DECISION
The Examiner’s decision rejecting claims 1, 3-22, 24, and 25 is
reversed.

REVERSED

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