Ex Parte Luick

Board of Patent Appeals and Interferences

Feb 22, 2012

11347414 (B.P.A.I. Feb. 22, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/347,414 02/03/2006 David A. Luick ROC920050277US1 3658
46797 7590 02/22/2012
IBM CORPORATION, INTELLECTUAL PROPERTY LAW
DEPT 917, BLDG. 006-1
3605 HIGHWAY 52 NORTH
ROCHESTER, MN 55901-7829
EXAMINER
FAAL, BABOUCARR
ART UNIT PAPER NUMBER
2189
MAIL DATE DELIVERY MODE
02/22/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte DAVID A. LUICK
____________

Appeal 2009-014962
Application 11/347,414
Technology Center 2100
____________

Before GREGORY J. GONSALVES, DAVID M. KOHUT, and
ERIC B. CHEN, Administrative Patent Judges.

GONSALVES, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2009-014962
Application 11/347,414

2
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the final rejection of
claims 1-12 and 25-34. (App. Br. 5.) Claims 13-24 were cancelled. (Id.)
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
The Invention
Exemplary independent claims 1 and 25 are as follows:
1. A method of prefetching data lines, comprising:
(a) fetching a first instruction line from a level 2 cache, wherein
the first instruction line comprises a plurality of instructions;
(b) extracting, from the first instruction line, an address identifying
a first data line containing data targeted by a data access instruction
contained in at least one of the first instruction line and a different
instruction line; and
(c) prefetching, from the level 2 cache, the first data line using the
extracted address.
25. A method of storing data target addresses in an instruction line,
the method comprising:
executing a plurality of instructions in the instruction line;
determining if one of the plurality of instructions accesses data in
a data line and results in a cache miss; and
if so, storing a data target address corresponding to the data line in
a location which is accessible by a prefetch mechanism.
The Examiner’s Rejections
The Examiner provisionally rejected claims 1-3, 6-8, 10, 11, 13-15,
18-20, 22, 24-28, 30-32, and 34 on the ground of nonstatutory obviousness-
Appeal 2009-014962
Application 11/347,414

3
type double patenting as being unpatentable over claims 1-3, 5-8, 9-11, 13-
22, and 24 of copending Application No. 11/347,412. (Ans. 3-6.)
The Examiner rejected claims 1-7, 11 and 12 under 35 U.S.C. §
102(b) as being anticipated by Emma (U.S. 2004/0015683 A1). (Ans. 6-8.)
The Examiner rejected claims 8, 10, 25-28, 30-34 under 35 U.S.C. §
103(a) for being unpatentable over Emma in view of Lee (U.S. 4,722,050).
(Ans. 8-12.)
The Examiner rejected claim 29 under 35 U.S.C. § 103(a) for being
unpatentable over Emma, in view Lee, and further in view of DeWitt (U.S.
2005/0154867). (Ans. 12-13.)

ISSUES
Appellant’s responses to the Examiner’s positions present the
following issues:
Did the Examiner establish that Emma discloses “extracting, from the
first instruction line, an address identifying a first data line containing data
targeted by a data access instruction contained in at least one of the first
instruction line and a different instruction line,” as recited in claim 1?
Did the Examiner establish that the combination of Emma and Lee
teaches or suggests “storing a data target address corresponding to the data
line in a location which is accessible by a prefetch mechanism,” as recited in
claim 25?

ANALYSIS
We have reviewed the Examiner’s anticipation and obviousness
rejections in light of Appellant’s arguments (Appeal Brief) that the
Appeal 2009-014962
Application 11/347,414

4
Examiner has erred. We disagree with Appellant’s conclusion regarding the
rejections of claims 1-12 and 25-34. We adopt as our own (1) the findings
and reasons set forth by the Examiner in the action from which this appeal is
taken and (2) the reasons set forth by the Examiner in the Examiner’s
Answer in response to the Appellant’s Appeal Brief. We concur with the
conclusion reached by the Examiner. Nonetheless, we highlight and address
specific findings and arguments regarding the recited “instruction line” and
“data line” for emphasis as follows.

Issue – Anticipation Rejection of Claims 1-7, 11, and 12
Appellant asserts that claim 1 is not anticipated because “Emma does
not disclose extracting, from an [sic] first instruction line, an address
identifying a first data line containing data targeted by a data access
instruction contained in at least one of the first instruction line and a
different instruction line.” (App. Br. 9 (emphasis omitted).) Appellant
argues that the claimed instruction line includes a plurality of instructions
and that Emma discloses only a single decoded instruction. (Id. at 10.) As
explained by the Examiner, however, Emma also discloses a memory line
that qualifies as the claimed first instruction line because it contains not only
the decoded instruction but also other instructions. (Ans. 14; citing Emma
¶ [0044] and Fig. 8.) Thus, we do not agree with Appellant.
Appellant also asserts that Emma does not “disclose extracting an
address of a first data line ….” (App. Br. 10.) In particular, Appellant
argues that the operand address disclosed in Emma does not qualify as the
claimed data line address because an operand is one data unit and, according
to Appellant’s specification, the data line includes “a plurality of data units.”
Appeal 2009-014962
Application 11/347,414

5
(Id.) Appellant’s argument, however, is not persuasive because it is not
commensurate with the scope of the claims because it attempts to improperly
incorporate limitations from the specification into the claims.
Accordingly, for these reasons and the reasons expressed in the
Examiner’s Answer, we sustain the anticipation rejection of claim 1, as well
as claims 2-7, 11, and 12 because Appellant did not set forth any separate
patentability arguments for those claims.

Issue – Obviousness Rejection of Claims 8, 10, and 25-34
Appellant asserts that independent claim 25 is not obvious because the
combination of Emma and Lee does not teach “… storing a data target
address corresponding to the data line in a location which is accessible by a
prefetch mechanism.” (App. Br. 11-12 (emphasis omitted).) In particular,
Appellant argues that Emma’s branch target address and branch instruction
do not qualify respectively, as the claimed data target address and data line
because “a data line (and more generally, data) is not the same as an
instruction.” (App. Br. 12.) Appellant further argues that Emma’s single
branch instruction cannot qualify as the claimed data line because the
claimed “data line includes a plurality of data units, which is not the same as
a branch instruction.” (Id.) As explained supra, however, Appellant’s
argument is not persuasive because it improperly attempts to incorporate
details of the data line from the specification into the claims. Moreover, one
of ordinary skill in the art, in light of Emma’s teaching of extracting the
address of an operand and Lee’s teaching of prefetching an address of an
instruction from a branch instruction, would have found it obvious to extract
Appeal 2009-014962
Application 11/347,414

6
and store a data target address corresponding to a data line, as required by
claim 25.
For these reasons and the reasons expressed in the Examiner’s
Answer, we sustain the Examiner’s obviousness rejection of claim 25 as
well as claims 8, 10, and 26-34 because Appellant did not set forth any
separate patentability arguments for those claims.
We will also sustain the Examiner’s provisional rejection of claims 1-
3, 6-8, 10, 11, 13-15, 18-20, 22, 24-28, 30-32, and 34 on the ground of
nonstatutory obviousness-type double patenting because Appellant did not
set forth any argument for this rejection. (See App. Br. 11-16.)

DECISION
We affirm the Examiner’s anticipation rejection of claims 1-7, 11, and
12, the obviousness rejection of claims 8, 10, and 25-34, and the provisional
rejection of claims 1-3, 6-8, 10, 11, 25-28, 30-32, and 34 on the ground of
nonstatutory obviousness type double patenting.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

tj