Ex Parte Lu et alDownload PDFPatent Trial and Appeal BoardJan 28, 201613039123 (P.T.A.B. Jan. 28, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 13/039, 123 03/02/2011 23494 7590 02/01/2016 TEXAS INSTRUMENTS IN CORPORA TED P 0 BOX 655474, MIS 3999 DALLAS, TX 75265 FIRST NAMED INVENTOR Jiong-Ping Lu UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. TI-37739.3 1187 EXAMINER STARK, JARRETT J ART UNIT PAPER NUMBER 2823 NOTIFICATION DATE DELIVERY MODE 02/01/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): uspto@ti.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte JIONG-PING LU and JIEJIE XU Appeal2014-003599 Application 13/039,123 Technology Center 2800 Before PETER F. KRATZ, KAREN M. HASTINGS, and WESLEY B. DERRICK, Administrative Patent Judges. KRATZ, Administrative Patent Judge. DECISION ON APPEAL This is a decision on an appeal under 35 U.S.C. § 134 from the Examiner's final rejection of claims 1-10. We have jurisdiction pursuant to 35 U.S.C. § 6. Appellants' claimed invention is directed to a method for making a transistor. Claims 1 and 6 are illustrative and reproduced below: 1. A method for making a transistor, comprising: providing a semiconductor substrate; forming a gate dielectric layer over said semiconductor substrate; forming a gate electrode layer over said gate dielectric layer; performing an ion implant on said gate electrode layer using F+ gas; Appeal2014-03599 Application 13/039, 123 and etching said implanted gate electrode layer and said gate dielectric layer to form a gate stack consisting of an amorphous gate electrode doped only with said p+ plus a gate dielectric that is free of said p+ dopant. 6. A method for making a transistor, comprising: providing a semiconductor substrate; forming a gate dielectric layer over said semiconductor substrate; forming a gate electrode layer over said gate dielectric layer; performing an ion implant into a top portion of said gate electrode layer using Sb+ gas; and etching said implanted gate electrode layer and said gate dielectric layer to form a gate stack consisting of a gate electrode doped only with said Sb+ plus a gate dielectric. The Examiner relies on the following prior art references as evidence in rejecting the appealed claims: Hao Kuroi Wang US 2005/0136579 Al US 6,300,664 B 1 US 2003/0227058 Al Jun.23,2005 Oct. 9, 2001 Dec. 11, 2003 The Examiner maintains the following grounds of rejection: Claims 1-5 stand rejected under 35 U.S.C. § 112, first paragraph as failing to comply with the written description requirement. Claim 1 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Hao. Claims 2-5 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Hao in view of Kuroi. Claims 6-10 stand rejected under 35 U.S.C. § 103(a) as being unpatentable over Wang. 2 Appeal2014-03599 Application 13/039, 123 We affirm the lack of written descriptive support rejection and the obviousness rejection over Wang. We reverse the obviousness rejections over Hao alone and Hao in view of Kuroi. Our reasoning follows. Written Description Rejection It is well settled that whether a specification complies with the written description requirement of 35 U.S.C. § 112, first paragraph, is a question of fact. Gentry Gallery Inc. v. Berkline Corp., 134 F.3d 1473, 1479 (Fed. Cir. 1998). The test for determining compliance with the written description requirement of 35 U.S.C. § 112, first paragraph for later claimed subject matter is whether the disclosure of the application as originally filed reasonably conveys to the artisan that the inventor had possession, as of the filing date, of the later claimed subject matter, rather than the presence or absence of literal support in the specification for the claim language. See Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555, 1563-64 (Fed. Cir. 1991) and In re Kaslow, 707 F.2d 1366, 1375 (Fed. Cir. 1983). The burden of showing that the claimed invention is not described in the specification rests on the Examiner. In re Alton, 76 F.3d 1168, 1175 (Fed. Cir. 1996); In re Wertheim, 541F.2d257, 262-265 (CCPA 1976). The Examiner meets this burden by adducing "evidence or reasons why persons skilled in the art would not recognize in the disclosure a description of the invention defined by the claims." Wertheim, 541 F.2d at 263-64. Here, the Examiner has determined that claims 1 through 5 fail to comply with the written description requirement because the Specification, as filed, furnishes no written descriptive support for forming a transistor with a gate dielectric that is free of F+ dopant as recited in claim 1 (Final 3 Appeal2014-03599 Application 13/039, 123 Office Action 2--4). In this regard, the Examiner has found that "[t]he originally filed Application is silent with regard to this limitation" and "fails to state the layer is free of F + [sic]" (Final Office Action 2 ). Moreover, the Examiner has determined that "it is reasonably expected and understood in the art that the F + dopants will migrate during subsequent annealing and are capable of reaching the gate dielectric layer as shown in the cited reference Hao et al." (Final Office Action 3). Thus, the Examiner has advanced evidence and reasoning as to why artisans would not recognize a description of the invention as now claimed in the originally filed disclosure. Appellants argue that paragraphs 23--42, and drawing Figures 2B-2G teach the negative limitation respecting the F+ dopant as regards the gate dielectric principally based on the ion implant region depicted in drawing Figs. 2B-2F (App. Br. 8-9). Appellants contend that the depiction of the ion implant region 195 in the cited drawing figures evinces that the implant region remains at the surface region of the gate electrode layer 115 and argue that there is no teaching of migration of the F+ dopant into the gate dielectric layer in their Specification, unlike the migration of dopant as disclosed by Hao (App. Br. 8-9). For reasons stated by the Examiner in the Answer, we are not persuaded that Appellants' argument indicates reversible error in the Examiner's factual determination as to a lack of written descriptive support in the Specification, as filed, for the new negative limitation in question (Ans. 3-5). The depiction of the implant region in the drawing Figures does not establish that migration of dopant from that implant region to the gate dielectric layer does not occur in the method of forming the transistor. While it may be possible to conduct the subsequent transistor formation 4 Appeal2014-03599 Application 13/039, 123 steps under conditions such that no migration of the p+ dopant into the gate dielectric layer occurs, Appellants have neither articulated what conditions are necessary nor that the necessary conditions were selected to prevent migration. In this regard, Appellants' Specification discloses that the fabrication of the transistor proceeds "with standard process steps" following the implantation (Spec. i-f 27). See, e.g., Lockwood v. Am. Airlines, Inc., 107 F.3d 1565, 1571-72 (Fed. Cir. 1997) ("One shows that one is "in possession" of the invention by describing the invention, with all of its claimed limitations, not that which makes it obvious"). Thus, on this record and upon due consideration of Appellants' arguments, we find that the weight of the evidence reasonably supports the Examiner's lack of written description determination with respect to claims 1-5. It follows that we shall affirm the Examiner's lack of written description rejection. Obviousness Rejections over Hao. As argued by Appellants, the Examiner has not established that Hao teaches or suggests forming a transistor with a gate dielectric that is free of p+ dopant in the obviousness rejection of claim 1 over Hao and/or established that Kuroi cures this deficiency in the applied teachings of Hao in the separate obviousness rejection of dependent claims 2-5 over the combined references' teachings (App. Br. 9-14). Accordingly, we reverse the Examiner's obviousness rejection of claim 1 over Hao and the Examiner's obviousness rejection of claims 2-5 over Hao in view of Kuroi. 5 Appeal2014-03599 Application 13/039, 123 Obviousness Rejection over Wang In the method of making a transistor of claim 6, an ion implant is conducted into the top portion of a gate electrode layer using Sb+ gas and etching of the gate electrode layer and gate dielectric layer is conducted after implantation to form a gate stack wherein the gate electrode of the gate stack is doped only with Sb+. Appellants argue that "Wang does not teach performing an ion implant into a top portion of the gate electrode layer using Sb+ gas" to form a gate stack having a gate electrode doped only with Sb+ as claimed because Wang employs a second ion implantation (App. Br. 15). This argument is not persuasive of reversible error in the Examiner's obviousness rejection of claim 6 because the referenced second ion implantation is directed at implanting a layer other than the gate stack gate electrode layer as pointed out by the Examiner (Ans. 5-6). Appellants present substantially the same argument against the Examiner's obviousness rejection over Wang made with respect to claim 6 as to dependent claims 7 through 10 (App. Br. 16-19). It follows that we shall affirm the Examiner's obviousness rejection of claims 6-10 over Wang. CONCLUSION The Examiner's decision to reject claim 1 under 35 U.S.C. § 103(a) as being unpatentable over Hao and to reject claims 2-5 under 35 U.S.C. § 103(a) as being unpatentable over Hao in view of Kuroi is reversed. 6 Appeal2014-03599 Application 13/039, 123 The Examiner's decision to reject claims 1-5 under 35 U.S.C. § 112, first paragraph as failing to comply with the written description requirement and to reject claims 6-10 under 35 U.S.C. § 103(a) as being unpatentable over Wang is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED tc 7 Copy with citationCopy as parenthetical citation