Ex Parte Lin et alDownload PDFPatent Trial and Appeal BoardMay 23, 201612964823 (P.T.A.B. May. 23, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/964,823 12/10/2010 112165 7590 05/25/2016 STATS ChipPAC/PATENTLAWGROUP: Atkins and Associates, P.C. 55 N. Arizona Place, Suite 104 Chandler, AZ 85225 FIRST NAMED INVENTOR YaojianLin UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 2515.0314 5495 EXAMINER CHIN, EDWARD ART UNIT PAPER NUMBER 2813 NOTIFICATION DATE DELIVERY MODE 05/25/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): main@plgaz.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte Y AOJIAN LIN, KANG CHEN, and JIANMIN FANG Appeal2014-005636 Application 12/964,823 Technology Center 2800 Before ADRIENE LEPIANE HANLON, CATHERINE Q. TIMM, and KAREN M. HASTINGS, Administrative Patent Judges. HASTINGS, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellants 1 seek our review under 35 U.S.C. § 134 of the Examiner's final decision rejecting claims 1-25 under 35 U.S.C. § 103(a) as unpatentable over the combined prior art of Meyer (U.S. Patent Publication No. US 2009/0085186 Al, published Apr. 2, 2009 "Meyer") in view of Cho (U.S. Patent No. US 6,400,021 Bl, issued June 4, 2002 "Cho") and further in view of Bauer et al. (U.S. Patent No. US 8, 173,488 B2, issued May 8, 2012 "Bauer"). We have jurisdiction over the appeal under 35 U.S.C. § 6(b). 1 The real party in interest is stated to be "STATS ChipPAC, Ltd." (Br. 1). Appeal2014-005636 Application 12/964,823 We AFFIRM. Claims 1 and 14 are illustrative of the claimed subject matter: 1. A method of making a semiconductor device, compnsmg: providing a semiconductor die; depositing an encapsulant over a first surface of the semiconductor die and around the semiconductor die; forming a first insulating layer in direct contact with a second surface of the semiconductor die opposite the first surface and in direct contact with the encapsulant including an interconnect site outside a footprint of the semiconductor die; removing less than an entirety of the first insulating layer within the interconnect site to expose the encapsulant while leaving a portion of the first insulating layer over a central region of the interconnect site; forming a first conductive layer over the first insulating layer and the exposed encapsulant within the interconnect site; forming a second insulating layer over the first conductive layer; and forming a bump over the first conductive layer, first insulating layer, and exposed encapsulant within the interconnect site. 14. A method of making a semiconductor device, compnsmg: providing a semiconductor die; depositing an encapsulant around the semiconductor die; forming a first insulating layer over the encapsulant and directly contacting the semiconductor die; forming an opening through the first insulating layer within an interconnect site over the encapsulant to expose less than an entirety of the encapsulant within the interconnect site; and forming a first conductive layer over the first insulating layer and exposed encapsulant. Independent claim 7 is directed to a method claim similar to claim 1 2 Appeal2014-005636 Application 12/964,823 and independent claim 21 is directed to a device claim corresponding to method claim 14 (Claims App'x). ANALYSIS We have thoroughly reviewed each of Appellants' arguments for patentability. However, we are in agreement with the Examiner that the claimed subject matter of representative claims 1 and 14 is unpatentable under § 103 in view of the applied prior art. Accordingly, we will sustain the Examiner's prior art rejection for essentially the reasons set out by the Examiner, including the response to argument section, and we add the following primarily for emphasis. In assessing whether a claim to a combination of prior art elements would have been obvious, the question to be asked is whether the improvement of the claim is more than the predictable use of prior art elements or steps according to their established functions. KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007). "[T]he analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim, for a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ." Id. at 418. We are not persuaded by Appellants' main argument that there is no reason to remove a portion as opposed to all of an insulating layer covering the encapsulant located at the interconnect site outside a footprint of the semiconductor die (e.g., Br. 15-16). 2 Likewise, Appellants' arguments that, 2 Appellants' basically rely upon the same arguments for each independent claim, although the arguments are repeated in separate sections of the brief (Br. 8-34). 3 Appeal2014-005636 Application 12/964,823 contrary to the Examiner's position, adding an etched insulating layer of Cho to Meyer would be technically incompatible with Meyer (Br. 14), are also not persuasive. As noted by the Examiner, Appellants' arguments mainly attack the references individually (e.g., Ans. 2, 3, 5, 6) 3. In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986) ("Non-obviousness cannot be established by attacking references individually where the rejection is based upon the teachings of a combination of references."). It is also noted that independent claims 14 and 21 do not recite that the interconnect site is outside the footprint of the semiconductor die; only independent claims 1 and 7 recite this feature. It is also well established that the "test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference .... Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art." See In re Keller, 642 F.2d 413, 425-26 (CCPA 1981); see also In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983) ("[I]t is not necessary that the inventions of the references be physically combinable to render obvious the invention under review."). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw 3 The Examiner relies upon Bauer to exemplify that it was known to form a conductive layer 219 over the insulating layer 215 within the interconnect site (e.g., Final Rej. 4, Bauer col. 7, 11. 19-25). However, the Examiner also notes that Meyer teaches this feature at Figs. 4F and 4H, disclosing layer 124 over die 2 (e.g., Ans. 8). Accordingly, it is not necessary to rely upon Bauer for this feature. 4 Appeal2014-005636 Application 12/964,823 therefrom. See In re Fritch, 972 F.2d 1260, 1264--65 (Fed. Cir. 1992); In re Preda, 401F.2d825, 826 (CCPA 1968). Appellants' Specification states: Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. (Spec. 6 ii 16). Appellants' Specification goes on to describe various front-end and back-end manufacturing techniques, including that: Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components. (Spec. 7 ii 18). Thus, Appellants describe that various techniques may be used for forming the various layers. In light of this general knowledge, as well as all the applied prior art evidence in the record, Appellants have not provided persuasive reasoning or credible evidence why one of ordinary skill in the art would not have, using no more than ordinary creativity, predictably used a known method of layer formation and removal as exemplified in Cho' s semiconductor die, for the partial removal of an insulating layer coating an encapsulant located at an interconnect site, for the interconnect site in Meyer 5 Appeal2014-005636 Application 12/964,823 that is located outside the footprint of the semiconductor die (e.g., Cho col. 4, 11. 4, 13-18, 57-58; Final Rej. 3; Ans. 3, 5-6; Br. generally). See KSR, 550 U.S. at 421 ("A person of ordinary skill is also a person of ordinary creativity, not an automaton."). Accordingly, we affirm the Examiner's§ 103 rejection of all the claims on appeal. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136. ORDER AFFIRMED 6 Copy with citationCopy as parenthetical citation