Ex Parte Lim et alDownload PDFPatent Trials and Appeals BoardJun 5, 201914396324 - (D) (P.T.A.B. Jun. 5, 2019) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE FIRST NAMED INVENTOR 14/396,324 10/22/2014 Kevin T. Lim 56436 7590 06/07/2019 Hewlett Packard Enterprise 3404 E. Harmony Road Mail Stop 79 Fort Collins, CO 80528 UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 84077713 9220 EXAMINER GIBSON, JONATHAN D ART UNIT PAPER NUMBER 2113 NOTIFICATION DATE DELIVERY MODE 06/07/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): hpe.ip.mail@hpe.com chris.mania@hpe.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte KEVIN T. LIM and AL VIN AUYOUNG Appeal2018-008197 Application 14/396,324 1 Technology Center 2100 Before ROBERT E. NAPPI, LINZY T. McCARTNEY, and MICHAEL T. CYGAN, Administrative Patent Judges. CYGAN, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF CASE Introduction Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's Final Rejection of claims 1-15. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 According to Appellants, Hewlett Packard Enterprise Development LP, a wholly-owned affiliate of Hewlett Packard Enterprise, and for which the general or managing partner is Enterprise DC Holdings LLC, is the real party in interest. App. Br. 3. Appeal2018-008197 Application 14/396,324 Disclosed Invention and Exemplary Claim The disclosed invention relates to checkpointing using a field programmable gate array (hereinafter "FPGA"). Abstract. Data within a region of a server can be checkpointed to memory while the checkpointed data is monitored using the FPGA. Id. Checkpointing can be performed by pausing an operation of a server, copying all of its data to non-volatile storage, and allowing the server to resume. Spec. ,r 13. An FPGA can be used to temporarily lock a hash table from access and checkpoint a particular region of the hash table by reading and copying values to memory. Id. at 15. The FPGA can be attached to the memory such that it can automatically track and capture accesses within each region, thereby maintaining a consistent view of each checkpoint. Id. at 18. Additionally, the FPGA can observe traffic to the regions by invalidating cache lines associated with a region that is checkpointing. Id. The FPGA can snoop on those cache lines, and the captured updates can be buffered and written to a log that can be replayed against a completed checkpoint to maintain a consistent state. Id. Independent claim 1 below is exemplary of the disclosed invention, and reads as follows: A computer-implemented method for checkpointing using a field programmable gate array (FPGA) comprising: temporarily locking a first region of data of a server to prevent access to the data in the first region while allowing access to data in other regions of the server; checkpointing the data in the first region of the server to memory while the first region is locked; subsequent to checkpointing the data in the first region, releasing the locking of the first region; and 2 Appeal2018-008197 Application 14/396,324 monitoring the checkpointed data of the first region using the FPGA, wherein the FPGA is coherently coupled to the memory such that the monitoring is performed automatically with the FPGA capturing accesses within the first region and the FPGA invalidates cache lines associated with the data in the first region of the server when it is checkpointing. Independent claims 7 and 12 recite limitations commensurate with the limitations recited in claim 1. Dependent claims 2---6, 8-11, and 13-15 each incorporate the limitations of their respective independent claims. Appellants do not argue any claims separately from claim 1. App. Br. passim. Examiner's Rejections The Examiner rejects claims 1--4, 7-13, and 15 under pre-AIA 35 U.S.C. § I03(a) as being obvious over the combination of Jouppi et al. (U.S. 2011/0113208 Al; published May 12, 2011) (hereinafter, "Jouppi"), Arnold et al. (U.S. Patent 5,175,837; published Dec. 29, 1992 (hereinafter "Arnold"), and Blair et al. (U.S. 2009/0070391 Al; published Mar. 12, 2009) (hereinafter "Blair"). The Examiner rejects claim 5 under pre-AIA 35 U.S.C. § I03(a) as being obvious over the combination of Jouppi, Arnold, and Blair, and further in view of Archer et al. (U.S. 2006/0236152 Al; published Oct. 19, 2006) (hereinafter "Archer"). The Examiner rejects claims 6 and 14 under pre-AIA 35 U.S.C. § I03(a) as being obvious over the combination of Jouppi, Arnold, and Blair, and further in view of Klein et al. (U.S. 2009/0265504Al; published Oct. 22, 2009) (hereinafter "Klein"). 3 Appeal2018-008197 Application 14/396,324 ANALYSIS We have reviewed the Examiner's rejections (Final Act. 2-18) in light of Appellants' contentions that the Examiner has erred (App. Br. 6-13). Further, we have reviewed the Examiner's response to Appellants' contentions. Ans. 3-5. We have also reviewed the Appellants' Reply Brief. Appellants contend that the combination of applied references does not teach or suggest at least "monitoring the checkpointed data ... automatically with the FPGA capturing accesses within the first region and the FPGA invalidates caches lines associated with the data ... while it is checkpointing," as recited in claim 1. App. Br. 7-11. The Examiner rejects claim 1 over the combination of Jouppi, Arnold, and Blair. Final Act. 2. The Examiner points to the teaching of Jouppi that the application being checkpointed suspends its execution during checkpoint operations, thereby preventing any cache lines from being created. Ans. 5. The Examiner further finds that suspending execution of the application controls access to the memory regions. Final Act. 4. The Examiner equates Jouppi's copying of data to memory to the claimed monitoring of the memory region, reasoning that "if the checkpoint management module is controlling the copying of data from one memory to the next, it inherently must be monitoring the memory region." Ans. 4. Appellants contend, inter alia, that the Examiner has not shown the combination of references to teach or suggest the claimed monitoring checkpointed data that captures accesses in a particular region of the memory and invalidates cache lines associated with the data in the first region of the server when it is checkpointing. App. Br. 9-11. Appellants disagree with the Examiner's interpretation of suspending an application 4 Appeal2018-008197 Application 14/396,324 being an invalidation of cache lines associated with the data, because merely suspending the application's execution would prevent any monitoring of traffic or accesses, including those that would be associated with invalidation of cache lines. Reply Br. 8. Appellants further argue that the claimed FPGA's invalidation of cache lines associated with a region is related to the FPGA's ability to snoop on the cache lines to observe traffic or to track and capture accesses within that region, and cannot be equated to suspending access to the region. Reply Br. 8. We find Appellants' argument persuasive. The Examiner relies on a teaching or suggestion in Jouppi of suspending the application whose data is being checkpointed. Under the Examiner's interpretation of Jouppi, the sole activity occurring during the checkpointing is the copying of checkpointed data. Ans. 4. From this, the Examiner has also found teachings or suggestions of monitoring the checkpointed data, capturing accesses within the region from which data is being checkpointed, and the invalidation of cache lines associated with data in the region being checkpointed. Final Act. 3--4. The Examiner finds that copying inherently requires monitoring of the data, and that suspending the application is the same as capturing accesses and invalidating cache lines. Ans. 4--5. However, we are persuaded by Appellants' arguments that the actions of monitoring data, capturing accesses, and invalidating cache lines are actions beyond the mere copying of data and suspending of the application being checkpointed. We agree with Appellants' reasoning that Jouppi's action of copying data in a suspended application, while meeting the limitation of checkpointing data in a temporarily locked region of data, does not sufficiently teach or suggest performing the additional acts of 5 Appeal2018-008197 Application 14/396,324 monitoring, capturing accesses, and invalidation of cache lines that are also required by claim 1. For the foregoing reasons, Appellants have shown that the Examiner erred in rejecting claim 1. Since the Examiner relies on the identical teachings or suggestions of the combination of Jouppi, Arnold, and Blair for claims 2--4, 7-13, and 15, the Appellants' arguments are also persuasive as to error in those obviousness rejections. In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992). With respect to claims 5, 6, and 14, rejected over the base references of Jouppi, Arnold, and Blair, further in view of Archer ( claim 5) or Klein ( claims 6 and 14 ), the Examiner has not shown either Archer of Klein to provide the teachings or suggestions found to be absent in the base references. Accordingly, Appellants' arguments are persuasive to error in the rejections of claims 5, 6, and 14. CONCLUSIONS We conclude that Appellants have shown that the Examiner has erred in rejecting independent claim 1, independent claims 7 and 12 that recite limitations commensurate with the limitations recited in claim 1, and dependent claims 2--4, 8-11, 13, and 15 under 35 U.S.C. § 103 as being obvious over the base combination of Jouppi, Arnold, and Blair. We further conclude that Appellants have shown error in the Examiner's rejections of claims 5, 6, and 14 as being obvious over the base combination of Jouppi, Arnold, and Blair in view of either Archer or Klein. In view of the foregoing, we reverse the Examiner's obviousness rejections of claims 1-15. 6 Appeal2018-008197 Application 14/396,324 DECISION We reverse the Examiner's rejections of claims 1-15 under pre-AIA 35 U.S.C. § 103(a). REVERSED 7 Copy with citationCopy as parenthetical citation