Ex Parte Leibowitz et alDownload PDFPatent Trial and Appeal BoardMar 31, 201612558133 (P.T.A.B. Mar. 31, 2016) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 12/558, 133 09/11/2009 38489 7590 04/04/2016 SILICON EDGE LAW GROUP, LLP 7901 Stoneridge Drive Suite 528 PLEASANTON, CA 94588 FIRST NAMED INVENTOR Brian S. Leibowitz UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. RA290.CIP1CIP1Cl.US 5825 EXAMINER YU,LIHONG ART UNIT PAPER NUMBER 2631 NOTIFICATION DATE DELIVERY MODE 04/04/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address( es): art@siliconedgelaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte BRIANS. LEIBOWITZ and BRUNOW. GARLEPP Appeal2014-003311 Application 12/558,133 Technology Center 2600 Before MAHSHID D. SAADAT, JOHNNY A. KUMAR, and JON M. JURGOV AN, Administrative Patent Judges. SAADAT, Administrative Patent Judge. DECISION ON APPEAL Appellants 1 appeal under 35 U.S.C. § 134(a) from a Final Rejection of claims 1, 2, 4, 5, 8-10, and 23-28.2 We have jurisdiction under 35 U.S.C. § 6(b ). We affirm. STATEMENT OF THE CASE 1 According to Appellants, the real party in interest is Rambus Incorporated (App. Br. 1 ). 2 Claims 11-22 have been canceled. The Examiner objected to claims 3, 6, and 7 as being dependent upon a rejected base claim, but otherwise noted that such claims contain allowable subject matter (Final Act. 8). Appeal2014-003311 Application 12/558,133 Introduction Appellant's invention relates to characterizing the margins of high- speed integrated circuits in digital receivers (Spec. i-f 12). Claim 1 is illustrative of the invention and reads as follows: 1. An integrated circuit receiver comprising: a data sampler operable to sample an input data signal according to a clock signal to produce a first series of data samples representing first and second logic values; a multiplexer having a first input operable to receive expected data, and a second input operable to receive a steady- state voltage representative of the first logic value, the multiplexer operable to convey a selected one of the expected data and the voltage representative of the first logic value as a multiplexer output; and an equalizer operable to receive the multiplexer output and to equalize the input data signal in dependence on the selected one. The Examiner's Rejections Claims 23-28 stand rejected under 35 U.S.C. § 112, first paragraph, as failing to comply with the enablement requirement (see Final Act. 4--5). Claims 1, 2, 4, 5, 8, 10, and 23-28 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Lee (US 6,055,119; iss. Apr. 25, 2000) (see Final Act. 5-8). Claim 9 stands rejected under 35 U.S.C. § 103(a) as unpatentable over Lee and Johnson (US 6,252,536 Bl; iss. June 26, 2001) (see Final Act. 8). Issues on Appeal Appellants' contentions present us with the following issues: 1. Did the Examiner err in rejecting claims 23-28 as failing to comply 2 Appeal2014-003311 Application 12/558,133 with the enablement requirement of 35 U.S.C. § 112, first paragraph? 2. Did the Examiner err by finding Lee teaches "a steady-state voltage representative of a first logic value," as recited in independent claim 1? 3. Did the Examiner err by finding Lee teaches "[a] sampler for sampling the input signal to produce a series of data samples," as recited in independent claim 23? 4. Did the Examiner err by finding the combination of Lee and Johnson teaches "[a] voltage representative of [a] first logic value is constant over multiple clock cycles," as recited in claim 9? ANALYSIS First Issue -Rejection under 112, first paragraph The Examiner has taken the position that the Specification does not contain sufficient information to enable the recitation of an equalizer operable to "equalize the input [data] signal,'' as recited in claim 23 (Final Act. 4--5). The Examiner states an equalizer performs equalization of its input signal, and because the claimed equalizer's input receives expected data signals and its output is coupled to the sampler input, the equalizer of claim 23 cannot equalize the input signal (Ans. 3--4). Appellants contend, as shown in their Figure 4, the claimed equalizer is a decision feedback equalizer (DFE), which provides corrective feedback to equalize an input signal by inputting historical data and outputting corrective feedback (App. Br. 6-7). Appellants conclude the recited DFE equalizer applies equalization at its output, and does not equalize its own input (App. Br. 7). 3 Appeal2014-003311 Application 12/558,133 In view of Appellants' explanation, we do not agree with the Examiner that the Specification lacks sufficient information to enable the recited equalizer operable to "equalize the input [data] signal." As such, under the factual situation presented in the present case, we find the subject matter of claims 23-28 is adequately enabled by the description of the invention provided in the Specification of the present application. Thus, we do not sustain the rejection of claims 23-28 under 35 U.S.C. § 112, first paragraph, as containing subject matter which was not described in the specification in such a way as to enable one skilled in the art to make and/or use the invention. Second Issue -Independent Claim 1 The Examiner finds Lee's digital multiplexer having logic high and logic low values, which are steady-state in their duration, teaches a multiplexer "operable to receive a steady-state voltage representative of [a] first logic value," as recited in independent claim 1 (Ans. 5). Appellants contend the multiplexer inputs of Lee are not steady-state voltages, because forcing the inputs to a steady-state input 0 or input 1 would be akin to disabling the circuit (App. Br. 8-10). Appellants argue Lee does not teach applying a steady-state voltage to the multiplexer for the duration of a margin test when that feedback value is of interest (Reply Br. 3--4). We are not persuaded of Examiner error. Appellants' argument regarding applying the steady-state voltage for the duration of a margin test is not commensurate with the scope of claim 1, which does not require any specific duration for the steady-state voltage. In fact, Appellants' Specification describes the steady-state voltage as a logic 1 or logic 0 (Spec. 4 Appeal2014-003311 Application 12/558,133 i-f 86). Therefore, we agree with the Examiner's finding that Lee teaches a multiplexer having steady-state voltage inputs of logic high ( 1) or logic low (0), the values being "steady-state" for each input sequence duration (Ans. 5). Thus, we sustain the Examiner's rejection of independent claim 1. Third Issue-Independent Claim 23 The Examiner finds the determiner circuit disclosed in Lee samples an input signal to produce a series logic high and logic low data, and therefore teaches the "sampler" of claim 23 (Ans. 6-7). Appellants contend Lee's analog-to-digital converter is the sampler that samples an input signal, while the determiner is for determining level values of the sampled data, and therefore the determiner cannot be considered a "sampler" (App. Br. 10; Reply Br. 4--5) We are not persuaded by Appellants' contentions. Appellants define "sampler'' as a circuit that periodically determines the probable value of an input signal to produce a digital value (App. Br. 10 (citing Spec. i-fi-13--4)), therefore, a sampler also has a function of "determining." Both the claimed sampler and Lee's determiner involve identification and correction of signal error based on a sampling clock (see Lee, col. 6, 11. 14--26 and col. 10, claim 11 ). Because the claimed sampler and the determiner perform similar functions and produce the same results as the determiner identified in Lee, we agree with the Examiner's finding that Lee's determiner meets the claimed sampler. In the Reply Brief, Appellants further contend that the Examiner has not shown where Lee teaches "expected data signals on the equalizer input," as recited in claim 23 (Reply Br. 4--5). This argument is entitled to no 5 Appeal2014-003311 Application 12/558,133 consideration because it was not presented for the first time in the opening brief. Optivus Tech., Inc. v. Ion Beam Appl'ns S.A., 469 F.3d 978, 989 (Fed. Cir. 2006) (argument raised for the first time in the reply brief that could have been raised in the opening brief is waived); accord Ex parte Borden, 93 USPQ2d 1473, 1473-74 (BPAI 2010) (informative opinion) (absent a showing of good cause, the Board is not required to address an argument newly presented in the reply brief that could have been presented in the principal brief on appeal); 37 C.F.R. § 41.41(b)(2) (any argument raised in the Reply Brief that was not raised in the Appeal Brief will not be considered by the Board absent a showing of good cause.) Fourth Issue -Dependent Claim 9 The Examiner finds Johnson's "PIX-GAIN" signal that is provided over multiple clock cycles teaches "[a] voltage representative of [a] first logic value is constant over multiple clock cycles,'' as recited in claim 9 (Final Act. 8). Appellants contend using Johnson's constant voltage in the multiplexer of Lee would deprive the multiplexer of the reference signal inputs and the determining data inputs, thus preventing Lee's circuit from functioning as intended (App. Br. 10-11). We are not persuaded of Examiner error, because we understand the Examiner's position to be Lee and Johnson teaches the claimed constant logic value in the case where the same logic high (1) or logic low (0) value is repeated (i.e., constant) over multiple clock cycles (see Final Act. 8), which does not deprive the multiplexer of any inputs. 6 Appeal2014-003311 Application 12/558,133 Remaining Claims No separate arguments are presented in support of the patentability of claims 2, 4, 5, 8, 10, and 24--28 (see App. Br. 10). Therefore we sustain their 35 U.S.C. § 103(a) rejection for the reasons stated above with respect to independent claims 1 and 23. DECISION The decision of the Examiner to reject claims 23-28 under 35 U.S.C. § 112, first paragraph, is reversed. The decision of the Examiner to reject claims 1, 2, 4, 5, 8-10, and 23- 28 under 35 U.S.C. § 103(a) is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). AFFIRMED 7 Copy with citationCopy as parenthetical citation