Ex Parte LEE et al

Patent Trial and Appeal Board

Jul 9, 2018

14628357 (P.T.A.B. Jul. 9, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/628,357 02/23/2015
9629 7590 07/11/2018
MORGAN LEWIS & BOCKIUS LLP (WA)
1111 PENNSYLVANIA A VENUE NW
WASHINGTON, DC 20004
FIRST NAMED INVENTOR
Y oungjang LEE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
065543-5419 5799
EXAMINER
GONDARENKO, NATALIA A
ART UNIT PAPER NUMBER
2891
NOTIFICATION DATE DELIVERY MODE
07/11/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@morganlewis.com
karen.catalano@morganlewis.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YOUNGJANG LEE, KYUNGMO SON, SEONGPIL CHO,
JAEHOON PARK, SOHYUNG LEE, SANGSOON NOH,
MOONHO PARK, SUNGJIN LEE,
SEUNGHYO KO, and MIJIN JEONG
Appeal2017-010947
Application 14/628,357
Technology Center 2800
Before RAEL YNN P. GUEST, N. WHITNEY WILSON, and
LILAN REN, Administrative Patent Judges.
WILSON, Administrative Patent Judge.
DECISION ON APPEAL
Appellants 1 appeal under 35 U.S.C. § 134(a) from the Examiner's
October 28, 2016 decision finally rejecting claims 1-5, 7, 9-11, 13, and
15-24. We have jurisdiction over the appeal under 35 U.S.C. § 6(b).
We affirm-in-part.
1 Appellants identify the real party in interest as LG Display Co. Ltd. (Br. 2).
Appeal2017-010947
Application 14/628,357
CLAIMED SUBJECT MATTER
Appellants' disclosure is directed to a thin film transistor substrate
which can be used for displays with low power consumption (Abstract,
Spec. ,r,r 8-9). The claimed substrate includes a substrate, a first thin film
transistor (TFT) including a first gate electrode disposed at a first area of the
substrate, and second TFT including a second gate electrode and an oxide
semiconductor layer disposed at a second area of the substrate (Abstract). A
nitride layer is disposed on only the first area of the substrate and covers the
first gate electrode, but not the second gate electrode (id.). The nitride layer
is disposed under an oxide layer which in tum is disposed over the first and
second gate electrodes and under the oxide semiconductor layer (id.).
Details of the claimed invention are set forth in independent claim 1, which
is reproduced below from the Claims Appendix of the Appeal Brief (with
the relevant phrases emphasized):
1. A thin film transistor substrate, comprising:
a substrate;
a first thin film transistor disposed at a first area of the
substrate, the first thin film transistor comprising:
a polycrystalline semiconductor layer;
a first gate electrode on the polycrystalline
semiconductor layer;
a first source electrode; and
a first drain electrode;
a second thin film transistor disposed at a second area of
the substrate, the second thin film transistor comprising:
a second gate electrode;
an oxide semiconductor layer on the second gate
electrode;
a second source electrode; and
a second drain electrode;
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Application 14/628,357
a nitride layer disposed on only the first area of the
substrate, the nitride layer covering the first gate electrode,
without covering the second gate electrode; and
an oxide layer disposed:
over the first gate electrode and the second gate
electrode; and
under the oxide semiconductor layer,
wherein the nitride layer is disposed under the oxide layer.
(Br. 29-30, Claim App'x). Independent claim 9 also is directed to a
thin film transistor substrate, and includes similar language to that
emphasized above (Id. at 32).
REJECTIONS
I. Claim 1 is provisionally rejected on the grounds of nonstatutory,
obviousness-type double patenting over claim 9 of Application No.
14/629,538 in view ofYan2 and Yang. 3
II. Claim 9 is provisionally rejected on the grounds of
nonstatutory, obviousness-type double patenting over claim 19 of
Application No. 14/629,538 in view of Yan and Yang.
III. Claims 1--4, 9, 10, 15-17, 19, 20, 22, and 23 are rejected under
35 U.S.C. § I03(a) as unpatentable over Yan in view of Yang, as evidenced
by Yamada 4 and Xiao. 5
2 Yan et al., US 2013/0168666 Al, published July 4, 2013.
3 Yang et al., US 2013/0015448 Al, published January 17, 2013.
4 Yamada et al. US 2004/0016924 Al, published January 29, 2004.
5 Xiao, Introduction to Semiconductor Manufacturing Technology, Second
Edition, Chapter 5 -Thermal Processes, Society of Photo-Optical Engineers
(2012), pp. 164---66 and 413-14.
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Application 14/628,357
IV. Claim 5 is rejected under 35 U.S.C. § I03(a) as unpatentable
over Yan in view of Yang, as evidenced by Yamada and Xiao, and further in
view of Isobe. 6
V. Claims 5, 7, 11, 13, 21, and 24 are rejected under 35 U.S.C.
§ I03(a) as unpatentable over Yan in view of Yang, as evidenced by
Yamada and Xiao, and further in view ofKato. 7
VI. Claims 17 and 18 are rejected under 35 U.S.C. § I03(a) as
unpatentable over Yan in view of Yang, as evidenced by Yamada and Xiao,
and further in view of Chen. 8
DISCUSSION
Rejections I. and II. Citing to MPEP §804(I)(B)(l ), Appellants
argue that if the statutory rejections are reversed on appeal, the provisional
non-statutory obviousness-type double patenting (POTDP) rejections should
also be reversed as they would be the only remaining rejections. Appellants
note that at least one of the pending applications which underlie the POTDP
rejections was filed after the application on appeal (Br. 8-9). There is no
substantive argument related to these rejections, which we therefore
summarily affirm.
Rejections III-VI. Because we decide this appeal based on a
limitation which is common to the two independent claims on appeal ( claims
1 and 9), we focus our discussion on the rejection of claim 1 over Yan in
view of Yang as evidenced by Yamada and Xiao.
6 Isobe et al., US 2006/0246644 Al, published November 2, 2006.
7 Kato, US 2005/0036382 Al, published February 17, 2005.
8 Chen et al., US 2012/0025320 Al, published February 2, 2012.
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Application 14/628,357
The Examiner finds that Yan discloses each element of claim 1,
except that "Yan does not specifically disclose a nitride layer disposed on
only the first area of the substrate, the nitride layer covering the first gate
electrode, without covering the second gate electrode, wherein the nitride
layer is disposed under the oxide layer" (Final Act. 7-8, citing Yan, FIG. IE,
,r,r 21-34).
The Examiner also finds that:
Yang teaches forming a semiconductor device comprising a
first thin film transistor (TFT) in a first region and a second
TFT in a second region (102); specifically, the first TFT
comprising a first gate electrode (18) and a first channel (12)
composed of polysilicon, and the first TFT comprising a second
gate electrode (142) and a second channel (20) composed of
oxide semiconductor; the second layer (222) that includes a
silicon nitride layer is formed to cover the first gate electrode
(18), without covering the second gate electrode (142). Further,
Yang teaches that the first dielectric layer (221) is to include a
silicon nitride layer and the second dielectric layer (222) is to
include a silicon oxide layer. Also, Yang teaches when the
inter-layered dielectric layer (222) is a silicon nitride layer,
hydrogen atoms tend to diffuse to the second channel layer (20)
during formation of the nitride layer (222) so that the nitride
layer (222) is removed to form an opening in the second region
(102) to diminish hydrogenation of the second channel layer
(20) composed of oxide semiconductor.
(Final Act. 8, internal citations and emphasis omitted). For ease of
reference, Yang's FIG. 13 is shown below:
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Application 14/628,357
IOI 102 k;: ................................................... >·!<.:················································· ,::,,.I
301
/,,--/ 22A
' !
14104) 14204\
JO
FIG. 13
,/
!'
/ 100
302
Yang's FIG. 13 is a schematic diagram illustrating a semiconductor device
according to an embodiment of Yang's invention.
The Examiner concludes that:
It would have been obvious to a person of ordinary skill in the
art before the effective filing date of the invention to modify the
thin film transistor substrate of Yan by forming nitride film
over the first gate electrode and without covering the second
gate electrode as taught by Yang to have a nitride layer
disposed on only the first area of the substrate, the nitride layer
covering the first gate electrode, without covering the second
gate electrode, wherein the nitride layer is disposed under the
oxide layer in order to provide nitride layer over the first
channel layer composed of polycrystalline silicon to obtain a
top gate type thin film transistor having improved
characteristics ... and to diminish hydrogenation of the second
channel layer composed of oxide semiconductor, thereby
ensuring semiconductor property of the second channel layer,
and thus to obtain a semiconductor device with advanced
electrical performance.
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Application 14/628,357
(Final Act. 9--10).
Appellants contend that none of the cited references renders obvious a
nitride layer, which is disposed only over the first area of the substrate and
covering the first gate electrode without covering the second gate electrode,
and is disposed under an oxide layer, which in tum is disposed under an
oxide semiconductor layer (Br. 13). According to Appellants, the Examiner
relies on the disclosure of Yang to suggest these features (id.). Appellants
contend the silicon nitride layer 221 or 222 of Yang cannot be disposed
under an oxide layer that in tum is disposed under second channel layer 20
(corresponding to the claimed oxide semiconductor layer).
With respect to the claim requirement that the nitride layer be
disposed under the oxide layer, the Examiner simply states "the secondary
reference Yang teaches forming the nitride layer under the oxide layer as
required by claim 1" without adequately identifying support in Yang for this
proposition (Ans. 3; see also Final Act. 8-10). Indeed, Yang teaches that
layer 221 or 222 could be a silicon nitride layer. Yet, layer 222, which is the
layer shown only over the first area of the substrate and covering the first
gate electrode without covering the second gate electrode, is disposed as the
very top layer and not taught as disposed under an additional oxide layer.
The Examiner has not explained why Yan in view of Yang teaches the exact
arrangement of nitride layer over only the first gate electrode, under an oxide
layer, which is under an oxide semiconductor layer, as recited in the claims.
The Examiner has the initial burden of establishing a prima facie case
of obviousness based on an inherent or explicit disclosure of the claimed
subject matter under 35 U.S.C. § 103. In re Oetiker, 977 F.2d 1443, 1445
(Fed. Cir. 1992) ("[T]he examiner bears the initial burden, on review of the
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Application 14/628,357
prior art or on any other ground, of presenting a prima facie case of
unpatentability."). To establish a prima facie case of obviousness, the
Examiner must show that each and every limitation of the claim is described
or suggested by the prior art or would have been obvious based on the
knowledge of those of ordinary skill in the art. In re Fine, 837 F.2d 1071,
1074 (Fed. Cir. 1988). In this instance, the evidence of record does not
adequately establish that the cited art would have made obvious the
limitation that the nitride layer is disposed under the oxide layer.
Accordingly, we reverse the rejection of independent claims 1 and 9
(which each contain the aforementioned limitation), as well as the rejections
of each of the dependent claims.
CONCLUSION
We AFFIRM the provisional rejection of claim 1 on the grounds of
nonstatutory, obviousness-type double patenting over claim 9 of Application
No. 14/629,538 in view of Yan and Yang.
We AFFIRM the provisional rejection of claim 9 on the grounds of
nonstatutory, obviousness-type double patenting over claim 19 of
Application No. 14/629,538 in view of Yan and Yang.
We REVERSE the rejection of claims 1--4, 9, 10, 15-17, 19, 20, 22,
and 23 under 35 U.S.C. § 103(a) as unpatentable over Yan in view of Yang,
as evidenced by Yamada and Xiao.
We REVERSE the rejection of claim 5 under 35 U.S.C. § 103(a) as
unpatentable over Yan in view of Yang, as evidenced by Yamada and Xiao, and
further in view of Isobe.
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Application 14/628,357
We REVERSE the rejection of claims 5, 7, 11, 13, 21, and 24 under
35 U.S.C. § 103(a) as unpatentable over Yan in view of Yang, as evidenced
by Yamada and Xiao, and further in view of Kato.
We REVERSE the rejection of claims 17 and 18 under 35 U.S.C. §
103(a) as unpatentable over Yan in view of Yang, as evidenced by Yamada
and Xiao, and further in view of Chen.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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