Ex Parte Labbe

Board of Patent Appeals and Interferences

Apr 3, 2009

11094064 (B.P.A.I. Apr. 3, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
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Ex parte ERIC LABBE
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Appeal 2009-0917
Application 11/094,0641
Technology Center 2800
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Decided:2 April 3, 2009
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Before MAHSHID D. SAADAT, ROBERT E. NAPPI, and MARC S.
HOFF, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF CASE
Appellant appeals under 35 U.S.C. § 134 from a Final Rejection of
claims 1-11. We have jurisdiction under 35 U.S.C. § 6(b).

1 The real party in interest is Texas Instruments Incorporated.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2009-0917
Application 11/094,064

We affirm.
Appellant’s invention relates to a circuit and method for providing a
strong pulldown for a power FET in an off state to avoid inadvertent or false
turn ons (Spec. 3). A low impedance FET is coupled to the gate of the low
side power FET in a switching half bridge (id.). The low impedance FET
may be triggered by a comparator with a certain threshold or by a current
source fed FET that obtains a certain switching threshold (Spec. 4).
Claims 1, 5, and 9 are exemplary:
1. A driver circuit for controlling a power FET, comprising:
a low impedance FET coupled to a gate of the power FET for
providing a low impedance path to a reference voltage for the gate of the
power FET when the low impedance FET is in a conductive state;
a control circuit coupled to the low impedance FET and operable to
turn the low impedance FET on and off; and
an enable signal in the control circuit operable to enable a conductive
state for the low impedance FET only by comparison of a gate voltage of the
power FET transitions with a predetermined threshold.

5. A method for driving a power FET, comprising:
transitioning the power FET from an on state to an off state;
applying a strong pull down to the gate of the power FET to maintain
the power FET in an off state, said strong pull down in addition to a pull
down of said transitioning the power FET from an on state to an off state;
transitioning the power FET from an off state to an on state; and
removing the strong pull down from the gate of the power FET to
permit the power FET to transition to the on state.

9. A circuit for driving a power FET, comprising:
a switch connected to a gate of the power FET for providing a strong
pull down on the gate when the switch is turned on;
an enable signal controlling the switch, operable to turn the switch on
after an interval when the power FET begins to turn off.
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Appeal 2009-0917
Application 11/094,064

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Kawakami US 5,625,312 Apr. 29, 1997

Claims 1-11 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kawakami.
Throughout this decision, we make reference to the Appeal Brief
(“Br.,” filed June 7, 2007) and the Examiner’s Answer (“Ans.,” mailed
October 19, 2007) for their respective details.
ISSUE
Appellant argues that because Kawakami’s low impedance transistor
20 is turned on by the switching of signal source 9, (a) it is not made
conductive by comparison of the gate voltage of the power FET with a
predetermined threshold; (b) it does not provide a strong pull down in
addition to a pull down of transitioning the power FET from an on state to an
off state; and (c) it is not controlled to turn on after an interval when the
power FET begins to turn off. In the Examiner’s view, the feedback loop of
Kawakami, including comparator 31, in combination with the power
transistor and low impedance transistor, enable Kawakami to meet the
claimed invention.
The respective contentions of Appellant and the Examiner thus
present us with the following issue:
Has Appellant shown that the Examiner erred in finding that
Kawakami teaches a control circuit that turns a low impedance transistor on
and off, enabling a conductive state for the low impedance transistor by
comparison of the gate voltage of a power transistor with a predetermined
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Appeal 2009-0917
Application 11/094,064

threshold, said low impedance transistor providing a strong pull down to the
gate of the power transistor when said power transistor transitions from an
on state to an off state, and said low impedance transistor being turned on
after an interval when the power transistor begins to turn off?
FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
The Invention
1. According to Appellant, the invention concerns a circuit and
method for providing a strong pulldown for a power FET in an off state to
avoid inadvertent or false turn ons (Spec. 3).
2. A low impedance FET is coupled to the gate of the low side
power FET in a switching half bridge (Spec. 3). The low impedance FET
may be triggered by a comparator with a certain threshold or by a current
source fed FET that obtains a certain switching threshold (Spec. 4).
Kawakami
3. Kawakami teaches “a control circuit for an insulated-gate
semiconductor device such as a power MOSFET and an IGBT used as a
switching element in motor driving inverters” (col. 1, ll. 6-9).
4. Kawakami teaches that signal source 9 produces an active low
output, with a high signal when the source is off (col. 7, ll. 26-27).
5. Kawakami teaches comparison of the gate voltage of IGBT 1
with threshold 32 at comparator 31, the output of which is fed to AND gate
33 to control transistor 34, itself connected to the gate of low impedance
pull-down transistor 20 (Fig. 2).
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Appeal 2009-0917
Application 11/094,064

PRINCIPLES OF LAW
Section 103 forbids issuance of a patent when “the differences
between the subject matter sought to be patented and the prior art are
such that the subject matter as a whole would have been obvious at
the time the invention was made to a person having ordinary skill in
the art to which said subject matter pertains.”

KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 127 S. Ct. 1727, 1734 (2007).
The question of obviousness is resolved on the basis of underlying factual
determinations including (1) the scope and content of the prior art, (2) any
differences between the claimed subject matter and the prior art, (3) the level
of skill in the art, and (4) where in evidence, so-called secondary
considerations. Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966). See
also KSR, 127 S. Ct. at 1734 (“While the sequence of these questions might
be reordered in any particular case, the [Graham] factors continue to define
the inquiry that controls.”)
In KSR, the Supreme Court emphasized “the need for caution in
granting a patent based on the combination of elements found in the prior
art,” id. at 1739, and discussed circumstances in which a patent might be
determined to be obvious. In particular, the Supreme Court emphasized that
“the principles laid down in Graham reaffirmed the ‘functional approach’ of
Hotchkiss, 11 How. 248.” KSR, 127 S. Ct. at 1739 (citing Graham v. John
Deere Co., 383 U.S. 1, 12 (1966) (emphasis added)), and reaffirmed
principles based on its precedent that “[t]he combination of familiar
elements according to known methods is likely to be obvious when it does
no more than yield predictable results.” Id The Court explained:
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of
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Appeal 2009-0917
Application 11/094,064

ordinary skill can implement a predictable variation, § 103
likely bars its patentability. For the same reason, if a technique
has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless
its actual application is beyond his or her skill.

Id. at 1740. The operative question in this “functional approach” is thus
“whether the improvement is more than the predictable use of prior art
elements according to their established functions.” Id.

ANALYSIS
CLAIMS 1-4
We select claim 1 as representative of this group, pursuant to our
authority under 37 C.F.R. § 41.37(c)(1)(vii).
Appellant argues that Kawakami does not suggest claim 1 because
npn transistor 20 is turned on by the switching of signal source 9 regardless
of the comparison of the gate voltage of the power transistor (IGBT 1) to
threshold 32 (Br. 5). Appellant’s argument is not persuasive of Examiner
error, however, because Kawakami teaches comparison of the gate voltage
of IGBT 1 with threshold 32 at comparator 31, the output of which is fed to
AND gate 33 to control transistor 34, itself connected to the gate of low
impedance pull-down transistor 20 (FF 5). Kawakami thus teaches enabling
a conductive state for low impedance transistor 20 by comparison of power
transistor gate voltage with a predetermined threshold, as recited in claim 1.
Because Appellant has not shown error in the Examiner’s rejection of
claim 1, we will sustain the rejection of claims 1-4 under 35 U.S.C. § 103.
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Appeal 2009-0917
Application 11/094,064

CLAIMS 5-8
We select claim 5 as representative of this group, pursuant to our
authority under 37 C.F.R. § 41.37(c)(1)(vii).
Appellant argues that Kawakami does not suggest claim 5 because
npn transistor 20 is turned on by the switching of signal source 9 and thus
does not apply a strong pull down in addition to the pull down of
transitioning the power transistor (IGBT 1) from an on state to an off state
(Br. 5). Appellant’s argument is not persuasive of Examiner error, because
when signal source output 9S switches to an off signal that is high (FF 4),
the gate of IGBT 1 goes low, transitioning the power transistor from on to
off. The output of comparator 31 will then transition to the on (high) state,
and combined with the high (“off”) output from signal source 9, AND output
33 will go high, turning on transistor 34 and then pull down transistor 20,
quickly pulling the gate of the power transistor IGBT 1 to ground (see Fig.
2). We therefore find that Kawakami does teach applying a strong pull down
to the gate of the power transistor, as recited in claim 5.
Because Appellant has not shown error in the Examiner’s rejection of
claim 5, we will sustain the rejection of claims 5-8 under 35 U.S.C. § 103.
CLAIMS 9-11
We select claim 9 as representative of this group, pursuant to our
authority under 37 C.F.R. § 41.37(c)(1)(vii).
Appellant argues that Kawakami does not suggest claim 9 because
transistor 20 “is turned on by the switching of signal source 9 . . . to turn off
IGBT 1 without any delay interval” (Br. 5), thus failing to meet the claim
limitation that a switch connected to the gate of the power transistor is
turned on “after an interval when the power FET begins to turn off.”
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Appeal 2009-0917
Application 11/094,064

Appellant’s argument is not persuasive of Examiner error. When
signal source 9S transitions to its high (off) state (FF 4), the gate voltage of
IGBT transitions from high to low, beginning the turn-off of the transistor,
and the output of comparator 31 will transition from low to high. AND gate
33 will then have two high inputs, and its output will transition to high,
turning on transistor 34, and then transistor 20 (Fig. 2). Comparator 31,
AND gate 33, and transistor 34, all interposed between the gate of IGBT 1
and the base of transistor 20, will each have some nonzero propagation
delay. Because of that combined propagation delay, transistor 20 (the
claimed “switch”) will be turned on after an interval (some amount of time)
when the power FET (IGBT 1) begins to turn off (see Kawakami col. 7, ll.
57-63).
Because Appellant has not shown error in the Examiner’s rejection of
claim 9, we will sustain the rejection of claims 9-11 under 35 U.S.C. § 103.
CONCLUSIONS OF LAW
Appellant has not shown that the Examiner erred in finding that
Kawakami teaches a control circuit that turns a low impedance transistor on
and off, enabling a conductive state for the low impedance transistor by
comparison of the gate voltage of a power transistor with a predetermined
threshold, said low impedance transistor providing a strong pull down to the
gate of the power transistor when said power transistor transitions from an
on state to an off state, and said low impedance transistor being turned on
after an interval when the power transistor begins to turn off.
ORDER
The Examiner’s rejection of claims 1-11 is affirmed.
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Appeal 2009-0917
Application 11/094,064

No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED

ELD

TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS, TX 75265
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