Ex Parte KRUTSCH et al

Patent Trial and Appeal Board

Sep 24, 2018

14746948 (P.T.A.B. Sep. 24, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/746,948 06/23/2015
34814 7590 09/26/2018
NXP-LARSON NEWMAN, LLP
6501 William Cannon Drive West
Austin, TX 78735
FIRST NAMED INVENTOR
ROBERT CRISTIAN KRUTSCH
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
AM21225ES 4218
EXAMINER
DEMETER, HILINA K
ART UNIT PAPER NUMBER
2674
NOTIFICATION DATE DELIVERY MODE
09/26/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ROBERT CRISTIAN KRUTSCH,
OLIVER BIBEL, and ROLF DIETER SCHLAGENHAFT
Appeal2018-003585
Application 14/746,948
Technology Center 2600
Before JOHN A. JEFFERY, DENISE M. POTHIER, and
JUSTIN BUSCH, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellants 1 appeal from the
Examiner's decision to reject claims 1-20. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm.
1 Appellants identify the real party in interest as NXP USA, Inc. App. Br. 1.
FREESCALE SEMICONDUCTOR, INC. is the Applicant for the instant
patent application. See Bib. Data Sheet.
Appeal2018-003585
Application 14/746,948
CLAIMED SUBJECT MATTER
Appellants' invention "relates ... to ... verifying the locations of
[graphics processing unit (GPU)] rendered objects in image space."
Spec. 1 :4--5. According to the Specification, a vertex shader unit receives a
stream of vertex data according to a vertex specification. Spec. 18: 1-2. The
vertex shader unit applies a transformation on each of the vertices in the
received stream of vertex data. Spec. 18:3--4. A comparator verifies the
integrity of at least a subset of the transformed vertex data on the basis of
reference data. Spec. 18:6-8. For example, the verification fails when the
subset of the transformed vertex data and the basis of reference data
mismatch. Spec. 18:9-10.
Claim 1 is representative and reproduced below:
1. An apparatus to verify the integrity of transformed vertex
data, said apparatus comprising:
a graphics processor comprising a hardware vertex shader,
wherein the hardware vertex shader is configured to
receive a stream of vertex data according to a vertex
specification, to apply a transformation on each of the
vertices in the received stream of vertex data to and to
output a stream of transformed vertex data;
a buffer coupled to the hardware vertex shader and
configured to buffer the transformed vertex data output by the
hardware vertex shader; and
a hardware comparator coupled to the buffer,
wherein the hardware comparator is configured to
verify the integrity of at least a subset of the transformed
vertex data on the basis of reference data and to issue a
fault indication signal in case the verification fails.
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Application 14/746,948
REJECTIONS
Claims 1--4, 8-13, 17, 18, and 20 stand rejected under 35 U.S.C. § 103
as being unpatentable over Avis (US 2010/0138376 Al; June 3, 2010) and
Kiel (US 2014/0146062 Al; May 29, 2014). Final Act. 4--11.
Claim 5-7, 14--16, and 19 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Avis, Kiel, and Rogers (US 2011/0115806 Al; May
19, 2011). Final Act. 11-16.
FACTS AND CONCLUSIONS
The Examiner's obviousness rejection relies principally on Avis for
teaching many of the recited limitations of independent claim 1, including,
among other things, (1) a hardware vertex shader configured to apply a
transformation on each vertex in a received stream of vertex data, (2) a
buffer configured to buffer the transformed vertex data, and (3) a hardware
comparator configured to verify the integrity of at least a subset of the
transformed vertex data on the basis of reference data. Final Act. 5.
Although the Examiner acknowledges that A vis does not teach the hardware
comparator configured to verify the integrity of at least a subset of the
transformed vertex data on the basis of reference data and to issue a fault
indication signal in case the verification fails, the Examiner cites Kiel for
teaching these features in concluding that the claim would have been
obvious. Id. at 5---6.
Appellants contend Kiel does not teach a hardware comparator
configured to verify an integrity of at least a subset of a transformed vertex
data on the basis of reference data and to issue a fault indication signal in
case the verification fails. App. Br. 5-7; Reply Br. 2--4. In particular,
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Application 14/746,948
Appellants assert Kiel's execution of a breakpoint that causes a signal to be
sent to a GPU to halt the GPU does not teach or suggest verifying an
integrity of at least a subset of a transformed vertex data on a basis of
reference data. App. Br. 6 ( citing Kiel ,r 20).
ISSUE
Under§ 103, has the Examiner erred in rejecting claim 1 by finding
that Avis and Kiel collectively would have taught or suggested a "hardware
comparator is configured to verify the integrity of at least a subset of the
transformed vertex data on the basis of reference data and to issue a fault
indication signal in case the verification fails," as recited in claim 1
(hereinafter "the disputed limitation")?
ANALYSIS
To resolve the question of patentability under§ 103, we begin by
construing the disputed limitation of independent claims 1, 10, and 18.
During examination, claims are given their broadest reasonable
interpretation consistent with the specification. See In re Am. Acad. of Sci.
Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). Here, the disputed
limitation recites two separate functions of a hardware comparator. Namely,
the hardware comparator is configured to ( 1) verify the integrity of at least a
subset of a transformed vertex data on a basis of reference data ("the
verifying limitation"), and (2) to issue a fault indication signal in case the
verification fails ("the issuing limitation").
The term "in case" of the disputed limitation is similar to the
conditional limitations discussed in Ex parte Schulhauser, No. 2013-007847,
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Appeal2018-003585
Application 14/746,948
2016 WL 6277792 (PT AB Apr. 28, 2016) (precedential) (holding that, in a
method claim, a step reciting a condition precedent does not need to be
performed if the condition precedent is not met). See also MANUAL OF
PATENT EXAMINING PROCEDURE (MPEP) § 2111.04(II) (9th ed. Rev.
08.2017, Jan. 2018) (citing Schulhauser). Although the limitations at issue
in Schulhauser were rendered conditional by the recitation of "if," see
Schulhauser at 6-8, we discern no meaningful distinction between the
recitations of "if' and the term "in case" recited in the independent claims in
this context.
Claims 10-17 are directed to a "method," i.e., a process. In accord
with our precedent, the issuing limitation of claims 10-1 7 need not occur to
satisfy the claim. See Schulhauser, 2016 WL 6277792, at *3-5. Claims 1-
9, however, are directed to an "apparatus," i.e., a machine; and claims 18-20
are directed to a "non-transitory, tangible computer readable storage medium
bearing computer executable instructions," i.e., an article of manufacture.
The broadest reasonable interpretation of an apparatus and an article of
manufacture claim2 with hardware that performs the issuing limitation,
which only needs to occur if a condition precedent is met, still requires
structure for performing the issuing limitation should the condition occur.
See Schulhauser, 2016 WL 6277792, at *14--15. Therefore, claims 1-9 and
18-20 have different scope than claims 10-17 because the structure, namely
2 We see no meaningful distinction between apparatus claims and article of
manufacture claims with respect to Schulhauser 's applicability.
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Application 14/746,948
the hardware configured to perform the recited issuing limitation, is required
regardless of whether the issuing limitation is actually performed.
Turning to the rejection, Appellants assert "[t]he Office acknowledges
that Avis fails to disclose [the verifying and issuing limitations] but asserts
that paragraph 0020 of Kiel discloses" the verifying and issuing limitations.
App. Br. 4.
We disagree with Appellants' characterization of the rejection. In the
rejection, the Examiner cites Avis for teaching or suggesting the verifying
limitation. Final Act. 5 (citing Avis ,r 105; Fig. 7). Specifically, the
Examiner finds that, after Avis' completed render pass (i.e., processing all
the geometry sent to the graphic pipeline), the results are available in the
frame buffer. Id. The Examiner finds A vis, therefore, teaches or suggests
the verifying limitation. Id. Such an explanation is enough to provide notice
of the rejection with sufficient particularity to allow Appellants a fair
opportunity to respond to the rejection. See 35 U.S.C. § 132; see also In re
Jung, 637 F.3d 1356, 1363 (Fed. Cir. 2011).
Therefore, contrary to Appellants' assertion, the Examiner finds A vis
or, alternatively, Kiel, teaches or suggests the verifying limitation. Compare
Final Act. 5 (finding Avis teaches or suggests the verifying limitation), with
id. at 6 (finding Kiel teaches or suggests the verifying limitation). We
emphasize the Examiner's alternative reliance on these two references, for
the teachings of one reference are technically cumulative to the other at least
with respect to the verifying limitation.
We see no error in the Examiner's reliance on paragraph 105 and
Figure 7 of A vis to teach or suggest the verifying limitation. We further
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note Appellants' argument that the Examiner fails to demonstrate the cited
disclosures teach or suggest a comparison of a subset of a transformed
vertex data to reference data is not commensurate with the scope of claim 1.
See Reply Br. 2 ( characterizing the integrity verification as being a
"comparison of the transformed vertex data to the reference data of claim
1. "). Claim 1, which recites no such comparison, recites "verify[ ing] the
integrity of at least a subset of the transformed vertex data on the basis of
reference data."
Therefore, Appellants' arguments regarding Kiel's alleged
shortcomings regarding the verifying and issuing limitations, App. Br. 5-7;
Reply Br. 2--4, do not show nonobviousness where, as here, the rejection is
based on the cited references' collective teachings-A vis for teaching or
suggesting the verifying limitation, and Kiel for teaching or suggesting the
issuing limitation. See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir.
1986).
Accordingly, we sustain the rejections of (1) independent claim 1; (2)
independent claims 10 and 18, which were rejected on substantially the same
bases as claim 1, see Final Act. 10-11; and (3) claims 2-9, 11-17, 19, and
20, which variously depend from claims 1, 10, and 18. 3
3 On the record before us, we presume that claim 19 is intended to depend
from independent claim 18, and not from itself. In the event of further
prosecution, the Examiner may wish to consider whether claim 19 ( and
claim 20, which depends therefrom) meets the requirement of 35 U.S.C.
§ 112(b).
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Application 14/746,948
DECISION
For the above reasons, the Examiner's decision to reject claims 1-20
is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 4I.50(f).
AFFIRMED
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