Ex Parte Kim

Patent Trial and Appeal Board

Aug 31, 2017

13804634 (P.T.A.B. Aug. 31, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/804,634 03/14/2013 Hye-Jeong KIM 0201-0655 1232
68103 7590 09/05/2017
Jefferson IP Law, LLP
1130 Connecticut Ave., NW, Suite 420
Washington, DC 20036
EXAMINER
ANYA, CHARLES E
ART UNIT PAPER NUMBER
2194
NOTIFICATION DATE DELIVERY MODE
09/05/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
u sdocketing @ j effersonip .com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HYE-JEONG KIM
Appeal 2017-005597
Application 13/804,6341
Technology Center 2100
Before LINZY T. McCARTNEY, NATHAN A. ENGELS, and
JAMES W. DEJMEK, Administrative Patent Judges.
DEJMEK, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1, 3—7, 9-14, 16—20, and 22—32. Claims 2, 8, 15, and 21 have been
canceled. See App. Br. 14—17. We have jurisdiction over the remaining
pending claims under 35 U.S.C. § 6(b).
We reverse.
1 Appellant identifies Samsung Electronics Co., Ltd. as the real party in
interest. App. Br. 2.
Appeal 2017-005597
Application 13/804,634
STATEMENT OF THE CASE
Introduction
Appellant’s disclosed and claimed invention is directed to a circuit for
processing data, the circuit including an Application Processor (AP), a
Communication Processor (CP), and a storage unit shared by the AP and CP.
Spec. 1^2, 31. In a disclosed embodiment, the storage unit comprises a first
region, a second region, and a third region. Spec. 131. The CP operatively
controls the first region, while both the CP and AP can access, read data
from, and write data to this region. Spec. H 31, 56. In addition, the CP can
access, read data from, and write data to the second region, whereas the AP
can access, read data from, and write data to the third region. Spec. 131.
Claim 1 is illustrative of the subject matter on appeal and is
reproduced below with the disputed limitation emphasized in italics:
1. A circuit for processing data, the circuit comprising:
an Application Processor (AP);
a Communication Processor (CP); and
a storage unit comprising:
at least a first region which the CP operatively
controls, and the AP and the CP access and from/to which
data of at least one of the AP and the CP is read/written
whereby the AP reads the data by one read operation,
a second region which the CP accesses and from/to
which data of the CP is read/written, and
a third region which the AP accesses and from/to
which data of the AP is read/written.
The Examiner’s Rejections
1. Claims 1, 3, 5, 7, 9-14, 16—20, and 22—27 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Nakagawa et al. (US
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Appeal 2017-005597
Application 13/804,634
2011/0249560 Al; Oct. 13, 2011) (“Nakagawa”); Ido (US 2010/0095072
Al; Apr. 15, 2010); and Applicants’ Admitted Prior Art (“AAPA”).
Final Act. 2—13.
2. Claims 4 and 6 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Nakagawa, Ido, AAPA, and Leucht-Roth (US
2013/0268689 Al; Oct. 10,2013). Final Act. 13-15.
3. Claims 28—32 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Nakagawa, Ido, AAPA, and Katou (US 2010/0227654
Al; Sept. 9, 2010). Final Act. 16—17.
Issue on Appeal2
Did the Examiner err by failing to make a sufficient finding with
respect to “at least a first region [(of a storage device)] which the CP
[(Communication Processor)] operatively controls,” as recited in claim 1?
ANALYSIS3
Appellant contends the Examiner erred in finding Nakagawa teaches
at least a first region of a storage unit operatively controlled by a
Communication Processor. App. Br. 6; Reply Br. 3. In particular, Appellant
2 We only address this issue, which is dispositive of the Examiner’s
rejections under 35 U.S.C. § 103(a). We do not address additional issues
raised by Appellant’s arguments related to these rejections.
3 Throughout this Decision, we have considered the Appeal Brief, filed
April 22, 2016 (“App. Br.”); the Reply Brief, filed February 16, 2017
(“Reply Br.”); the Examiner’s Answer, mailed December 16, 2016 (“Ans.”);
and the Final Office Action, mailed November 23, 2015 (“Final Act.”), from
which this Appeal is taken.
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Application 13/804,634
argues Nakagawa generally discloses the sharing of a buffering IC between a
Communication Processor and an Application Processor but fails to teach
the buffering IC is operatively controlled by the Communication Processor,
as required by claim 1. App. Br. 6 (citing Nakagawa 56—59). Further,
Appellant argues “the mere provision of a common region of (shared)
memory as in Nakagawa, does not describe separately or in combination
with other cited references, control of the region and more specifically,
control of the region by the CP as recited.” Reply Br. 3 (brackets omitted).
Nakagawa describes a scenario wherein a communication scheme is
adopted having a high data transfer rate such that the amount of data to be
transferred from the Communication Processor to the Application Processor
is too great for the Application Processor to process the received data
sufficiently. Nakagawa 1 5. Nakagawa further explains when the data
processing speeds of the Communication Processor and Application
Processor are different, and particularly when the downstream processor has
a slower data processing speed, data outputted from the processor on the
upstream side cannot be fully processed and buffer overrun occurs.
Nakagawa 17. To address the identified issue, Nakagawa is generally
directed to providing “a CPU connection circuit which is a circuit to be
employed by two CPUs by alternately conducting a changeover between two
buffers disposed therebetween to prevent an event that data processing
cannot be fully executed by the CPU on the receiving side.” Nakagawa 19.
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Application 13/804,634
Figure 1 of Nakagawa is illustrative and is reproduced below.
F I G. 1
3
Figure 1 of Nakagawa illustrates the connections between two CPUs—a
Communication CPU (CCPU) and an Application CPU (ACPU)—and a
buffering IC. Nakagawa H 34—35. Nakagawa describes the buffering IC as
comprising a circuit including two buffers, wherein:
the circuit being connected between two CPUs for relaying data
transfer from one of the CPUs to the other one thereof,
characterized by including: means for monitoring whether or not
an amount of data stored by a transmission-side CPU in either
one of the buffers reaches a predetermined threshold value; and
means for requesting, when the amount of data stored by the
transmission-side CPU in the buffer reaches the threshold value,
a reception-side CPU to acquire the data stored in the buffer and
changing the data storage destination of the transmission-side
CPU to the other one of the buffers, the threshold value being a
value more than a unit quantity of data which the transmission-
side CPU sends to the buffer.
Nakagawa 110. Further, as illustrated in Figure 1, a data acquisition request
signal is asserted when a data read buffer satisfies a condition for the ACPU
to read data from the buffering IC. Nakagawa 1 56. Additionally, an
overrun interrupt signal may be generated by the buffering IC and sent to the
ACPU when an overrun condition (i.e., data loss) occurs. Nakagawa 1 57.
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Application 13/804,634
Nakagawa also discloses the buffering IC “possesses a function of flow
control signal controllable from the ACPU.” Nakagawa 159. By
controlling this signal, retransmission of data can be notified to the CCPU.
Nakagawa 1 59.
The Examiner finds, inter alia, Nakagawa teaches the claimed
Application Processor (i.e., ACPU); Communication Processor (i.e., CCPU);
and storage unit (i.e., buffering IC). Final Act. 3. Further, the Examiner
finds Nakagawa teaches the buffering IC comprises at least a first region
which the Communication Processor operatively controls, and the
Application Processor and Communication Processor access, and from/to
which data of at least one of the Application Processor and the
Communication Processor is read/written, as recited in claim 1. Final
Act. 3. In response to Appellant’s argument regarding the teaching of
whether the Communication Processor operatively controls the buffering IC,
the Examiner explains ‘“operatively control’ implies a common region of
memory which the Application Processor and Communication Processor
(CP) share and from which they (AP and CP) may read and write data.”
Ans. 22.
Claims are interpreted with an eye toward giving effect to all terms in
the claim. See, e.g., Elekta Instrument S.A. v. O.U.R. Sci. Int’l, Inc., 214
F.3d 1302, 1305, 1307 (Fed. Cir. 2000). Here, the disputed limitation
already provides that the first region of the storage unit is shared between the
Application Processor and Communication Processor (i.e., “the AP and the
CP [(may)] access”) and that at least one may read and write data to the
shared region (i.e., “from/to which data of at least one of the AP and the CP
is read/written”). In addition, the claim requires the Communication
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Application 13/804,634
Processor operatively control the storage unit (i.e., buffering IC). As
described in the Specification, the Communication Processor’s operative
control of the first region of the storage unit is separate and distinct from its
ability to access, read data from, and write data to the first region. See Spec.
56—58. The Examiner’s proposed construction for “operatively controls”
is already recited by the remaining claim language. Thus, the Examiner’s
construction renders the rest of the claim limitation superfluous. See
Mangosoft, Inc. v. Oracle Corp., 525 F.3d 1327, 1130—31 (Fed. Cir. 2008)
(rejecting claim construction that would render a claim term superfluous).
Further, the Examiner has not provided sufficient persuasive evidence
or explanation that the Communication Processor in Nakagawa operatively
controls the buffering IC. Rather, Nakagawa discloses it is the Application
Processor that controls a flow control signal/fimction of the buffering IC.
See Nakagawa 1 59.
For the reasons discussed supra, and constrained by the record before
us, we do not sustain the Examiner’s rejection of independent claim 1. For
similar reasons, we do not sustain the Examiner’s rejection of independent
claims 7, 14, 20, and 27, which recite similar limitations. Further, we do not
sustain the Examiner’s rejections under 35 U.S.C. § 103(a) of claims 3—6, 9—
13, 16—19, 22—26, and 28—32, which depend therefrom.
DECISION
We reverse the Examiner’s decision rejecting claims 1, 3—7, 9-14,
16-20, and 22-32.
REVERSED
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