Ex Parte Khater

Patent Trial and Appeal Board

Nov 15, 2012

11161286 (P.T.A.B. Nov. 15, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte MARWAN H. KHATER
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Appeal 2010-006520
Application 11/161,286
Technology Center 2800
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Before KALYAN K. DESHPANDE, JASON V. MORGAN, and
JOHN G. NEW, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Introduction
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s Final
Rejection of claims 1, 2, 4, 6, 8–15, and 19. Claims 3, 5, 7, and 16–18 are
canceled. See App. Br. 2. We have jurisdiction under 35 U.S.C. § 6(b)(1).
We affirm.
Invention
The invention relates to methods of fabricating a bipolar transistor for
improved isolation, passivation, and critical dimension control. See Title.
These methods can include disposing an additional layer of silicon nitride
over a passivation oxide layer as a sacrificial layer which protects the
passivation oxide layer from being reduced in thickness or being undercut
during a reactive ion etch (RIE) process and one or more cleaning processes
conducted after the RIE process. See Abstract.
Exemplary Claim
1. A method of making a bipolar transistor, comprising:

forming a portion of said bipolar transistor including a
collector region, an intrinsic base layer overlying said collector
region, a mandrel having an upwardly rising wall overlying a
first portion of said intrinsic base layer, with an etch stop layer
formed between said intrinsic base layer and said mandrel, a
replaceable dielectric spacer disposed on said wall of said
mandrel, and a raised extrinsic base layer overlying a second
portion of said intrinsic base layer, wherein said etch stop
includes a layer of oxide deposited to overlie said intrinsic base
layer and a layer of nitride deposited to overlie said layer of
oxide;

etching to remove said mandrel to form an emitter
opening having an upwardly rising wall by processing
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including reactive ion etching said mandrel selective to a
material of said etch stop layer; and

forming a replacement dielectric spacer on said wall of
said emitter opening and forming an emitter layer separated
from said raised extrinsic base layer by at least said replacement
dielectric spacer.

App. Br. 11 (Claims App’x) (emphasis added).
Rejections
The Examiner rejects claims 1, 4, 6, 8, 10–13, and 19 under 35 U.S.C.
§ 103(a) as being unpatentable over Khater (US 2004/0188797 A1; Sept. 30,
2004; filed Mar. 28, 2003) (“Khater ’797”) and Yi (US 2004/0157387 A1;
Aug. 12, 2004). Ans. 5–12.
The Examiner rejects claim 2 under 35 U.S.C. § 103(a) as being
unpatentable over Khater ’797, Yi, and Appellant’s Admitted Prior Art
(Spec. fig. 3A and ¶ [0003]) (“AAPA”). Ans. 12.
The Examiner rejects claims 14 and 15 under 35 U.S.C. § 103(a) as
being unpatentable over Khater ’797, Yi, and Trivedi (US 6,524,901 B1;
Feb. 25, 2003). Ans. 13 – 15.
The Examiner rejects claim 9 under 35 U.S.C. § 103(a) as being
unpatentable over Khater ’797, Yi, Trivedi, and AAPA. Ans. 15 – 18.
ISSUE
Does Yi teach away from modifying Khater ’797 to include “wherein
said etch stop includes a layer of oxide deposited to overlie said intrinsic
base layer and a layer of nitride deposited to overlie said layer of oxide,” as
recited in claim 1?
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ANALYSIS
The Examiner finds that Khater ’797 teaches most of the recitations of
claim 1, including a third silicon oxide layer OX3 that forms an etch stop
layer. See Ans. 5 – 6 (citing, e.g., Khater ’797 fig. 2Q and ¶ [0038]). The
Examiner acknowledges that Khater ’797 fails to expressly disclose
“wherein said etch stop includes a layer of oxide deposited to overlie said
intrinsic base layer and a layer of nitride deposited to overlie said layer of
oxide,” as recited in claim 1. See Ans. 6. Thus, the Examiner relies on Yi,
which is directed to a method for manufacturing self-aligned BiCMOS, to
illustrate that this claimed feature is well-known in the art. See id.
Specifically, the Examiner relies on Yi’s teaching of applying a thin oxide
layer 120 and a nitride layer 122 on a SiGe base layer 118 to teach or
suggest an etch stop that includes a layer of oxide deposited on an intrinsic
base layer and a nitride layer deposited on the oxide layer. See Ans. 6 (citing
Yi figs. 2 – 3 and ¶¶ [0045] – [0046]).
Appellant contends that the Examiner erred in relying on the
combined teachings of Khater ’797 and Yi, arguing that “Yi’s description of
the formation of and extent of oxide and nitride layers teach away from the
method described in the ’797 Patent [Application] and, therefore, cannot be
combined with the ’797 Patent [Application] to render the claims obvious.”
App. Br. 7. Specifically, Appellant argues that:
Yi’s requirement that the blanket oxide and nitride layers 120,
122, 124 of Yi be present adjacent to the polysilicon plug 132
when the polysilicon plug is removed teaches away from the
claimed fabrication method (cl.l) that requires a “raised
extrinsic base layer” be disposed overlying a second portion of
an intrinsic base. The blanket oxide and nitride layers 120, 122,
124 of Yi are insulating layers which preclude conductive
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connection. A raised extrinsic base layer would not be a “raised
extrinsic base layer” if it is not conductively connected to the
intrinsic base layer (See Fig. 2P and ¶[0049] of the ’797 Patent
[Application]), because then, the transistor would not operate.
App. Br. 9.
The Examiner correctly notes that the test for whether the
combination of Khater ’797 and Yi is obvious is not whether the features of
Yi can be bodily incorporated into the method taught or suggested by Khater
’797. Rather, the test is what the combined teachings of Khater ’797 and Yi
would have suggested to an artisan of ordinary skill. See Ans. 18–19; see
also In re Keller, 642 F.2d 413, 425 (CCPA 1981). We find that Appellant’s
arguments are not persuasive of error because “the exact process that Yi uses
the taught etch stop layers for need not be bodily incorporated into the ’797
patent” application. Ans. 19.
Furthermore, we find that the Examiner properly relies on Yi for the
limited teaching of using an oxide layer with an overlying nitride layer to
form multiple etch stop layers of different etch rates. See Ans. 6 – 7 and 19.
The Examiner correctly finds that Yi provides evidence that “multiple etch
stop layers of different etch rates are well known in the art and the
application of said multiple etch stop layers provides the predictable result of
allowing for enhanced etching control.” Ans. 19. We agree with the
Examiner. Modifying Khater ’797 to replace the third silicon oxide layer
OX3 etch stop layer with Yi’s oxide and nitride layers represents alteration
of Khater ’797 by mere substitution of one element for another element
known in the field to yield a predictable result. See KSR Int’l, Co. v. Teleflex,
Inc., 550 U.S. 398, 416 (2007).
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Appellant also does not persuasively show that Yi “criticizes,
discredits, or otherwise discourages” the use of multiple oxide and nitride
etch stop layers in other fabrication processes, such as the one described in
Khater ’797. See In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004).
Therefore, we agree with the Examiner that Yi does not teach away from
modifying Khater ’797 to include “wherein said etch stop includes a layer of
oxide deposited to overlie said intrinsic base layer and a layer of nitride
deposited to overlie said layer of oxide,” as recited in claim 1.
Accordingly, we sustain the Examiner’s 35 U.S.C. § 103(a) rejection
of claim 1, and of claims 2, 4, 6, 8–15, and 19, which are not argued
separately with sufficient specificity. See App. Br. 9–10.
DECISION
The Examiner’s decision to reject claims 1, 2, 4, 6, 8–15, and 19 is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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