Ex Parte Johansson

Board of Patent Appeals and Interferences

Apr 13, 2009

10829694 (B.P.A.I. Apr. 13, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte TED JOHANSSON
Appeal 2009-2248
Application 10/829,6941
Technology Center 2800
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Decided:2 April 13, 2009
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Before JOSEPH F. RUGGIERO, SCOTT R. BOALICK, and
MARC S. HOFF, Administrative Patent Judges.

BOALICK, Administrative Patent Judge.

1 Application filed April 22, 2004. Application 10/829,694 is a continuation
of International Application No. PCT/SE02/01914, filed Oct. 21, 2002,
which claims priority to Swedish Application No. 0103806-6, filed Nov. 15,
2001. The real party in interest is Infineon Technologies AG.
2 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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DECISION ON APPEAL
This is an appeal under 35 U.S.C. § 134(a) from the final rejection of
claims 1-26, all the claims pending in the application. We have jurisdiction
under 35 U.S.C. § 6(b).
We reverse.

STATEMENT OF THE CASE
Appellant’s invention relates to the formation of a PMOS varactor in a
semiconductor process flow. (Spec. paragraph [0002].)

Claim 1 is exemplary:
1. A method in the fabrication of an integrated circuit
including a PMOS varactor and a vertical bipolar npn transistor,
said method comprising the steps of:

providing a p-doped substrate;

simultaneously forming a buried n+-doped region for the
PMOS varactor and a buried n+-doped region for the npn
transistor in said substrate;

simultaneously forming in said substrate an essentially n-
doped region above the buried n+-doped region for the PMOS
varactor and an n-doped region above the buried n+-doped
region for the npn transistor;

simultaneously forming field isolation areas, in a
horizontal plane, around said n-doped regions;

forming a PMOS gate region on said essentially n-doped
region for the PMOS varactor;

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forming a p-doped base in the n-doped region above the
buried n+-doped region for the npn transistor and an n-doped
emitter in the p-doped base;

simultaneously forming an n-doped contact to the buried
n+-doped region for the PMOS varactor and an n-doped
collector contact to the buried n+-doped region for the npn
transistor; said contacts being separated from, in a horizontal
plane, said n-doped regions; and

forming a gate terminal connected to the PMOS gate
region and a bulk terminal connected to the n-doped bulk
contact.

The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Rahim et al. US 5,405,790 Apr. 11, 1995

Claims 1-26 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Rahim.

Rather than repeat the arguments of Appellant or the Examiner, we
make reference to the Brief and the Answer for their respective details.
Except as noted in this decision, Appellant has not presented any substantive
arguments directed separately to the patentability of the dependent claims.
Only those arguments actually made by Appellant have been considered in
this decision. Arguments that Appellant did not make in the Brief have not
been considered and are deemed to be waived. See 37 C.F.R.
§ 41.37(c)(1)(vii).
Appeal 2009-2248
Application 10/829,694

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ISSUE
Appellant argues that Rahim does not disclose all the limitations of
independent claims 1 and 16. (Br. 5-6.) In particular, Appellant argues that
Rahim does not teach “forming a PMOS gate region on said essentially
n-doped region for the PMOS varactor,” as recited in claims 1 and 16. (Br.
5.)
Appellant's arguments present the following issue:
Has Appellant shown that the Examiner erred in rejecting claims 1-26
under 35 U.S.C. § 102(b)?
The resolution of this issue turns on the following subsidiary issue:
Has Appellant shown that the Examiner erred in finding that Rahim
teaches “forming a PMOS gate region on said essentially n-doped region for
the PMOS varactor”?

FINDINGS OF FACT
The record supports the following findings of fact (FF) by a
preponderance of the evidence.

1. Rahim is directed to “a method of manufacturing a varactor that is
readily incorporated into a high performance integrated circuit
process.” (Col. 1, ll. 31-34.) Rahim discloses “a varactor-BICMOS
semiconductor structure 10” which includes three separate devices:
MOS region 12, varactor region 13, and bipolar region 14. MOS
region 12, varactor region 13, and bipolar region 14 are
subcomponents of semiconductor structure 10. (Col. 1, ll. 60-66.)
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The method of Rahim provides for “extremely high performance
varactor-BICMOS technology wherein a high performance varactor
device is combined with a bipolar device and an advanced CMOS
device.” (Col. 9, ll. 50-54.)
2. Figures 1, 3, 5, 7 and 9 represent MOS region 12; Figures 2, 4, 6, 8,
and 10 represent varactor region 13 and bipolar region 14. (Col. 1,
ll. 63-64.)
3. Rahim discloses that MOS region 12 includes source and drain
regions 108 (Col. 8, ll. 55-57) and gate electrodes 88. (Col. 9, ll. 3-6).

PRINCIPLES OF LAW
Anticipation is established when a single prior art reference discloses
expressly or under the principles of inherency each and every limitation of
the claimed invention. Atlas Powder Co. v. IRECO Inc., 190 F.3d 1342,
1347 (Fed. Cir. 1999); In re Paulsen, 30 F.3d 1475, 1478-79
(Fed. Cir. 1994).

ANALYSIS
On the record before us, we agree with Appellant (Br. 5-6) that Rahim
does not disclose all the limitations in independent claims 1 and 16. In
particular, Rahim does not teach “forming a PMOS gate region on said
essentially n-doped region for the PMOS varactor.”

Claim 1
The Examiner found that the limitation of “forming a PMOS gate
region on said essentially n-doped region for the PMOS varactor” is
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illustrated in Figure 8 of Rahim. (Ans. 3.) The Examiner has also found
that the recitation of “[a] varactor (10, 115, 122) … formed using a
BICMOS process flow” in Rahim’s abstract teaches a PMOS varactor.
(Final Office Action 7-8.) We do not agree.
We do not find that Figure 8 of Rahim teaches a PMOS varactor.
Rahim discloses “a varactor-BICMOS semiconductor structure 10” that
includes three separate devices: MOS region 12, varactor region 13, and
bipolar region 14. (FF 1.) Figure 8 illustrates varactor region 13 and bipolar
region 14, rather than MOS region 12. (FF 2.) Rahim does not teach that
varactor region 13 is a PMOS varactor because varactor region 13 lacks the
necessary components for a MOS device (i.e., source, drain and gate). (Cf.
FF 3.) Likewise, Rahim does not teach that MOS region 12 is a varactor
because Rahim teaches a separate varactor region 13. (FF 1.)
The Examiner improperly relied upon the language “[a] varactor (10,
115, 122) … formed using a BICMOS process flow” for the disclosure of a
PMOS varactor. (Final Office Action 7-8.) When the Abstract is read in the
context of the entire Specification, Rahim teaches that varactor region 13 is a
separate device from MOS region 12, where both devices are
subcomponents of semiconductor structure 10. (FF 1.)
The Examiner also found that the limitation of “an n-doped contact to
the buried n+-doped region for the PMOS varactor” corresponds to source
and drain regions 108 of Rahim. (Final Office Action 2.) However, as
discussed previously, Rahim provides no teaching of a PMOS varactor.
Therefore, Appellant has shown that the Examiner erred in finding
that Rahim teaches “forming a PMOS gate region on said essentially n-
doped region for the PMOS varactor,” as recited in claim 1. In addition,
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Appellant has shown that the Examiner erred in finding that Rahim teaches
“an n-doped contact to the buried n+-doped region for the PMOS varactor,”
as recited in claim 1.

Claim 16
In addition to the findings discussed above with respect to claim 1, the
Examiner also found that, for the limitation of “forming a PMOS gate region
on said essentially n-doped region for the PMOS varactor,” the claimed
“PMOS gate region” corresponds to gate electrodes 88 of Rahim and the
claimed “essentially n-doped region” corresponds to N wells 28. (Ans. 6.)
However, as discussed previously, Rahim provides no teaching of a PMOS
varactor.
Therefore, Appellant has shown that the Examiner erred in finding
that Rahim teaches the limitation of “forming a PMOS gate region on said
essentially n-doped region for the PMOS varactor,” as recited in claim 16.
Therefore, we conclude that Appellant has shown that the Examiner
erred in rejecting independent claim 1 as well as claims 2-15, which depend
from claim 1, under 35 U.S.C. § 102(b). Independent claim 16 recites
limitations similar to those discussed with respect to independent claim 1,
and we find the Examiner erred in rejecting independent claim 16 and claims
17-26, which depend from claim 16, for the same reasons discussed with
respect to claim 1.

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CONCLUSION
Based on the findings of facts and analysis above, we conclude that
Appellant has shown that the Examiner erred in rejecting claims 1-26 for
anticipation under 35 U.S.C. § 102(b).

DECISION
The rejection of claims 1-26 for anticipation under 35 U.S.C. § 102(b)
is reversed.

REVERSED

ack

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