Ex Parte Jayaseelan et al

Patent Trial and Appeal Board

Jul 31, 2018

13739161 (P.T.A.B. Jul. 31, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
13/739, 161 01/11/2013 Ramkumar Jayaseelan
109712 7590 08/02/2018
Advanced Micro Devices, Inc.
c/o Davidson Sheehan LLP
6836 Austin Center Blvd.
Suite 320
Austin, TX 78731
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
1458-120158 1373
EXAMINER
HUSON, ZACHARY K
ART UNIT PAPER NUMBER
2181
NOTIFICATION DATE DELIVERY MODE
08/02/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@ds-patent.com
AMD@DS-patent.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RAMKUMAR JAY ASEELAN and RA VINDRA N. BHARGA VA
Appeal2018-001007
Application 13/739,161 1
Technology Center 2100
Before TERRENCE W. McMILLIN, KARA L. SZPONDOWSKI, and
SCOTT B. HOWARD, Administrative Patent Judges.
McMILLIN, Administrative Patent Judge.
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(a) of the final
rejection of claims 1--4, 6-16, 18-23, and 25. Claims 5, 17, and 24 stand
objected to as being dependent upon a rejected base claim but are otherwise
allowable. Final Act. 7. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.
1 According to Appellants, the real party in interest is Advanced Micro
Devices, Inc. App. Br. 1.
Appeal2018-001007
Application 13/739,161
THE CLAIMED INVENTION
The present invention relates generally to "thread selection at a
processor." Spec. ,r 1. Independent claims 1 and 10 are directed to methods;
independent claim 13 is directed to a processor; and independent claim 20 is
directed to a non-transitory computer readable medium. App. Br. 12, 14--16.
Claim 1, reproduced below, is representative of the claimed subject
matter:
1. A method, comprising:
selecting one of a first thread and a second thread for
processing at a first stage of an instruction pipeline of a processor
based on a first branch prediction confidence for the first thread
and a second branch prediction confidence for the second thread,
the processor prioritizing the thread having the higher of the first
and second branch prediction confidence.
REJECTION ON APPEAL
Claims 1--4, 6-16, 18-23, and 25 stand rejected under 35 U.S.C.
§ I03(a) as being unpatentable over Gschwind et al. (US 2009/0193231 Al;
published July 30, 2009) ("Gschwind") and Burcea et al. (US 2013/0007423
Al; published Jan. 3, 2013) ("Burcea"). Ans. 2.
ANALYSIS
Claims 1--4, 7-16, and 19-23
Claim 1 recites "the processor prioritizing the thread having the higher
of the first and second branch prediction confidence."
The Examiner finds Burcea's lower confidence branches being given
lower priority teaches the processor prioritizing the thread having the higher
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Application 13/739,161
confidence. Ans. 3 ( citing Burcea ,r 19). According to the Examiner, it
would have been obvious to combine Burcea with Gschwind because Burcea
teaches a "well-known technique intended to reduce the proportion of
instructions fetched and executed from a wrong path." Ans. 3.
Appellants contend replacing "Gschwind's teachings of prioritizing
lower confidence levels with Burcea's prioritizing of higher confidence
branches would change the operations of and render Gschwind
unsatisfactory for its intended purpose (i.e., prioritizing low confidence level
branches to fetch the redirect instructions address sooner rather than later)."
App. Br. 8; see Reply Br. 3--4 (citing In re Gordon, 733 F.2d 900, 902 (Fed.
Cir. 1984)).
We are not persuaded by Appellants' arguments. We agree with the
Examiner that Gschwind' s intended purpose is "improving thread selection
in a multithreaded processor of an information handling system," and that
Burcea's "prioritizing threads with a higher confidence" does not render
Gschwind unsatisfactory for this purpose. Ans. 8-9. Contrary to
Appellants' arguments, Gschwind's disclosure is broader than simply
"prioritizing low confidence level branches to fetch the redirect instructions
address sooner rather than later." See, e.g. Gschwind ,r,r 5-6, claims 1, 8, 15.
Rather, as cited by the Examiner (Ans. 8), Gschwind is directed toward a
"thread priority controller" that "changes a priority of the particular
instruction thread in response to the branch issue information." Gschwind
,r 6.
As cited by the Examiner (Ans. 8), Burcea discloses "an approach
where threads with low confidence in-flight branches are given lower
priority for instruction fetch" and a technique "has also been implemented
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Application 13/739,161
that favors threads with more L 1 data cache misses in an attempt to provide
more resources for slow threads." Burcea ,r 19. In other words, Burcea
teaches prioritizing threads with higher confidence (i.e., giving low
confidence threads lower priority), and also prioritizing threads with lower
confidence (i.e., favoring threads with more LI data cache misses).
Therefore, we agree with the Examiner that Burcea teaches "many
alternative methods of achieving the same goal of effectively utilizing
resources to further improve efficiency of multi-thread systems," including
prioritizing threads with higher confidence as claimed. Ans. 9.
Appellants have not provided persuasive argument or evidence that
the claimed "processor prioritizing the thread having the higher of the first
and second branch prediction confidence" is not taught or otherwise
suggested by Burcea's giving lower priority to low confidence threads.
Accordingly, we sustain the 35 U.S.C. § 103 rejection of independent
claim 1, as well as the rejections of independent claims 10, 13, and 20, and
dependent claims 2--4, 7-9, 11, 12, 14--16, 19, and 21-23, not separately
argued. See App. Br. 9, 10.
Claims 6, 18, and 25
Claim 6 recites "determining a plurality of branch predictions for the
first thread based on a plurality of branch prediction techniques; and
identifying the first branch prediction confidence based on a number of the
plurality of branch predictions."
The Examiner finds Gschwind teaches different branch prediction
techniques such as using a branch predictor, using a confidence queue for
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Application 13/739,161
each particular branch instruction, and based on the type of branch
instruction. Ans. 9 ( citing Gschwind ,r,r 21, 23, 24 ).
Appellants contend Gschwind teaches "comparing whether a single
branch prediction confidence exceeds a predetermined threshold," but not
"that the branch prediction confidence is based on the number of multiple
branch predictions from different branch prediction techniques that exceed a
threshold number." App. Br. 10.
We are not persuaded by Appellants' arguments. As cited by the
Examiner (Ans. 9), Gschwind teaches a "branch predictor 310" (Gschwind
,r 21 ), using a "confidence queue" to store confidence information "that
indicates the level of confidence in the prediction of the particular branch
that branch predictor 310 provides" (Gschwind ,r 23), and basing "the
confidence in a branch prediction on a confidence value derived at branch
instruction prediction time" (Gschwind ,r 24). In other words, Gschwind
teaches various branch prediction techniques used to identify branch
prediction confidence.
Appellants have not rebutted the Examiner's findings, or provided any
persuasive argument or evidence that the claimed "determining a plurality of
branch predictions for the first thread based on a plurality of branch
prediction techniques; and identifying the first branch prediction confidence
based on a number of the plurality of branch predictions" is not taught or
otherwise suggested by Gschwind' s use of various branch prediction
techniques to identify branch prediction confidence.
Accordingly, we sustain the 35 U.S.C. § 103 rejection of dependent
claim 6 and commensurate dependent claims 18 and 25.
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Application 13/739,161
DECISION
The Examiner's rejection of claims 1--4, 6-16, 18-23, and 25 under
35 U.S.C. § 103 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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