Ex Parte Jacob et al

Patent Trial and Appeal Board

Jul 28, 2016

13613508 (P.T.A.B. Jul. 28, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/613,508 09/13/2012
10742 7590 08/01/2016
GLOBALFOUNDRIES INC.
c/o Amerson Law Firm, PLLC
2500 Fondren Road, Suite 220
Houston, TX 77063
FIRST NAMED INVENTOR
Ajey P. Jacob
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
2162.216900/CU 183 3101
EXAMINER
NGUYEN, SOPHIA T
ART UNIT PAPER NUMBER
2822
NOTIFICATION DATE DELIVERY MODE
08/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
uspto@amersoniplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte AJEY P. JACOB, WITOLD P. MASZARA, and
KEREM AKARVARDAR
Appeal2015-001954
Application 13/613,508
Technology Center 2800
Before TERRY J. OWENS, BEYERL YA. FRANKLIN, and
JEFFREY R. SNAY, Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-12, 19 and 20. We have jurisdiction under
35 U.S.C. § 6(b).
The Invention
The Appellants claim a method for forming first and second FinFET
[fin-shaped active area field effect transistor (Spec. 3:12-15)] devices.
Claim 1 is illustrative:
1. A method of forming first and second FinFET devices
in and above a semiconducting substrate, comprising:
forming a first patterned mask layer above said substrate
that exposes a first region of said substrate where said first
Appeal2015-001954
Application 13/613,508
FinFET device will be formed and masks a second region of
said substrate where said second FinFET device will be formed;
with said first patterned mask layer in position, forming a
first fin for said first FinFET device, wherein said first fin is
comprised of a first semiconductor material that is different
from the material of said semiconducting substrate;
removing said first patterned masking layer;
after removing said first patterned masking layer,
forming a second patterned masking layer that masks said first
region of said substrate and exposes said second region of said
substrate where said second FinFET device will be formed; and
after forming said first fin, and with said second
patterned masking layer in position, forming a second fin for
said second FinFET device, wherein said second fin is
comprised of a second semiconductor material that is (a) in
contact with said material of said semiconducting substrate,
(b) different from the material of said semiconducting substrate
and ( c) different from said first semiconductor material.
Chidambarrao
Lee
The References
US 7,198,995 B2
US 2011/0121406 Al
The Rejections
Apr. 3, 2007
May 26, 2011
The claims stand rejected as follows: claims 1-5 and 7-11 under
35 U.S.C. § 102(b) over Chidambarrao, claims 6 and 12 under
35 U.S.C. § 103 over Chidambarrao, and claims 19 and 20 under
35 U.S.C. § 103 over Chidambarrao in view of Lee.
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Appeal2015-001954
Application 13/613,508
OPINION
We reverse the rejections. We need address only the independent
claims, i.e., claims 1 and 7 .1 Claim 1 requires "with said first patterned
mask layer in position, forming a first fin for said first FinFET device" and
"with said second patterned mask layer in position, forming a second fin for
said second FinFET device," and claim 7 requires "with said first patterned
mask layer in position, performing at least one process operation through
said first patterned mask to form a first fin for said first FinFET device" and
"with said second patterned mask layer in position, performing at least one
process operation through said second patterned mask to form a second fin
for said second FinFET device".
"Anticipation requires that every limitation of the claim in issue be
disclosed, either expressly or under principles of inherency, in a single prior
art reference." Corning Glass Works v. Sumitomo Elec. U.S.A., Inc., 868
F.2d 1251, 1255-56 (Fed. Cir. 1989).
Chidambarrao forms an nFET (n-type PET) and a pFET (p-type PET)
by applying a pFET mask ( 45) to the portion of a silicon layer (20) at which
the pFET is to be formed, growing an epitaxial Ge layer (30) on the portion
of the silicon layer (20) at which the nFET is to be formed, removing the
pFET mask (45), covering the Ge layer (30) with an nFET mask (35),
growing an Si:C layer ( 40) on the portion of the silicon layer (20) at which
the pFET is to be formed, removing the nFET mask (35), and annealing the
structure to form an SiGe nFET (50) and an Si:C pFET (55) (col. 5, 1. 47 -
1 In the rejections under 35 U.S.C. § 103 the Examiner does not rely upon
any obviousness rationale regarding the independent claims' limitations
(Ans. 5-6).
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Appeal2015-001954
Application 13/613,508
col. 6, 1. 31; Figs. 7-10). Chidambarrao then applies a hard mask (70) over
the structure and performs a sidewall image transfer and etch to form nFET
fins (75) andpFET fins (80) (col. 6, 1. 54-col. 7, 1. 10; Figs. 11-13).
Thus, Chidambarrao does not form the fins (75, 80) while the
masks (35, 45) are in position as required by the Appellants' claims 1 and 7
but, rather, forms the fins (75, 80) after the masks (35, 45) have been
removed.
The Examiner argues that Chadambarrao's Ge layer (30) and Si:C
layer ( 40), which are formed while the masks (35, 45) are in position, are
fins "[b ]ecause 'fin' is any structure having a width and a thickness and
extends vertically from a substrate" (Ans. 6), and that "[t]he layers [30]
and [40] are initial fins which are made larger to form the final fins 75
and 80" (Id.).
The Examiner provides no support for the relied-upon definition of
"fin". The ordinary meaning of "fin" is "[a] projecting flat plat or structure,
as a cooling fin. "2 The meaning of "fin" indicated by the Appellants'
Specification3 is consistent with that meaning. Those meanings of "fin"
indicate that the Examiner's asserted meaning of that term is incorrect.
2 MCGRAW-HILL DICTIONARY OF SCIENTIFIC AND TECHNICAL TERMS 755
(5th ed. 1994).
3 "In contrast to a PET, which has a planar structure, there are so-called
3D devices, such as an illustrative FinFET device, which is a 3-dimensional
structure. More specifically, in a FinFET, a generally vertically positioned
fin-shaped active area is formed and a gate electrode encloses both sides and
an upper surface of the fin-shaped active area to form a tri-gate structure so
as to use a channel having a 3-dimensional structure instead of a planar
structure .... Unlike a planar PET, in a FinFET device, a channel is formed
perpendicular to a surface of the semiconducting substrate so as to reduce
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Appeal2015-001954
Application 13/613,508
The Examiner, therefore, has not established that Chidambarrao
discloses every limitation of the Appellants' independent claims, either
expressly or under principles of inherency.
For the above reasons we reverse the rejections under
35 U.S.C. §§ 102(b) and 103.
DECISION/ORDER
The rejections of claims 1-5 and 7-11under35 U.S.C. § 102(b) over
Chidambarrao, claims 6 and 12 under 35 U.S.C. § 103 over Chidambarrao,
and claims 19 and 20 under 35 U.S.C. § 103 over Chidambarrao in view of
Lee are reversed.
It is ordered that the Examiner's decision is reversed.
REVERSED
the physical size of the semiconductor device" (Spec. 3:10-18; Fig. 3H
(fins 24)).
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