Ex Parte Hwang et alDownload PDFPatent Trial and Appeal BoardJul 25, 201310883950 (P.T.A.B. Jul. 25, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/883,950 07/02/2004 Sang-Won Hwang 5649-1320 5979 7590 07/26/2013 D. Randal Ayers Myers Bigel Sibley & Sajovec, P.A. P.O. Box 37428 Raleigh, NC 27627 EXAMINER PATEL, KAUSHIKKUMAR M ART UNIT PAPER NUMBER 2188 MAIL DATE DELIVERY MODE 07/26/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte SANG-WON HWANG and JIN-YUB LEE ____________________ Appeal 2011-003182 Application 10/883,950 Technology Center 2100 ____________________ Before JOHN A. JEFFERY, MARC S. HOFF, and PATRICK M. BOUCHER, Administrative Patent Judges. BOUCHER, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-003182 Application 10/883,950 2 STATEMENT OF THE CASE Introduction Appellants appeal under 35 U.S.C. § 134(a) from a rejection of claims 1–5, 7–16, 18–20, 26, and 27. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. Illustrative Claim The claimed subject matter relates to memory and information processing systems that buffer memories (Spec., p. 1, ll. 6–8). A memory device includes a nonvolatile memory such as a flash device and a volatile memory such as a buffer, with the buffer memory acting as an intermediary through which data are temporarily stored when being transferred to or from the nonvolatile memory (id., p. 6, ll. 1–9). A portion or all of the buffer memory may be designated as a locked region that is write-protected so that information stored therein may not be overwritten (id., p. 6, ll. 15–19). Claim 1 is illustrative and is reproduced below with certain limitations emphasized: 1. A memory device comprising: a non-volatile memory; a volatile memory that is configured to store data that is to be stored in the non-volatile memory and data read from the non-volatile memory; and at least one control circuit that receives information appointing an address of the volatile memory as a write- protected region so that information stored therein may not be overwritten; wherein the volatile memory comprises a buffer memory that is configured to store data that is received before the data is stored in the non-volatile memory, wherein the at least one control circuit comprises: Appeal 2011-003182 Application 10/883,950 3 an address register for storing the address to appoint the write-protected region of the volatile memory in response to a control signal from a state machine; a status register for storing information indicating whether the volatile memory is partially or wholly appointed to the write-protected region; a comparator for deciding whether an input address is identical to the address stored in the address register; and a signal generator for generating a flag signal that indicates whether the input address corresponds to the write-protected region. References The prior art relied upon by the Examiner in rejecting the claims on appeal is: Larsen Kasai Miyake Tamura US 6,154,819 US 6,229,731B1 US 6,868,472B1 US 7,114,117B2 Nov. 28, 2000 May 8, 2001 Mar. 15, 2005 (filed Sep. 28, 2000) Sep. 26, 2006 Chevallier US 2004/0083346 A1 (filed Feb. 27, 2002) Apr. 29, 2004 Rejections The Examiner made the following rejections: Claims 1–5, 7–11, 26, and 27 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Tamura, Miyake, Larsen, and Kasai (Ans. 4–9, 14–15). Claims 12–15 and 18–20 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Tamura, Miyake, and Chevallier (Ans. 9–13). Claim 16 stands rejected under 35 U.S.C. § 103(a) as being unpatentable over Tamura, Miyake, Chevallier, and Kasai (Ans. 13–14). Appeal 2011-003182 Application 10/883,950 4 ANALYSIS Claims 1 and 9–11 Appellants make the following contentions with respect to the rejection of independent claim 1. 1. Appellants contend that the Examiner erred because Miyake fails to disclose “appointing an address of the volatile memory as a write- protected region so that information stored therein may not be overwritten,” as recited in claim 1 (emphasis added) (Br. 5–6). 2. Appellants contend that the Examiner erred because one of skill in the art would not combine Tamura and Miyake in the manner suggested (Br. 6–7). 3. Appellants contend that the Examiner erred because the cited registers of Larsen are not configured “for storing the address to appoint the write-protected region of the volatile memory in response to a control signal from a state machine,” as recited in claim 1 (emphasis added) (Br. 7). 4. Appellants contend the Examiner erred because the state machine of Kasai does not provide a control signal to an address register, as recited in claim 1 (Br. 7). 5. Appellants contend the Examiner erred because none of the cited references disclose the “status register” recited in claim 1. With respect to the first contention, we are not persuaded that the Examiner erred. Miyake teaches a cache memory controller (Miyake, col. 1, ll. 10–13) that implements a “cache lock instruction” that acts to inhibit the replacement of cache blocks back to main memory (id., col. 10, ll. 6–17) under certain conditions such as cache misses. Appellants’ contention Appeal 2011-003182 Application 10/883,950 5 characterizes this cache lock instruction as write-protecting a permanent memory rather than write-protecting the cache memory (Br. 5). We disagree. In the context of Miyake’s disclosure of cache-memory control, the inhibition of “replacing all the cache blocks to the main memory” (Miyake, col. 10, ll. 10–11) acts to protect the affected portions of the cache memory from being overwritten by replacement data. This at least suggests the claim limitation of “appointing an address of the volatile memory as a write-protected region so that information stored therein may not be overwritten.” With respect to the second contention, we are not persuaded that the Examiner erred. While Appellants’ argument emphasizes differences in the functionality of buffer memories and cache memories (Br. 6), the Examiner finds that the buffer memory of Tamura and the cache memory of Miyake have relevant common characteristics: both act as intermediary volatile memories that manage data being written to or read from a nonvolatile memory (Ans. 19, 20). We agree with the Examiner’s reasoning and conclude that an ordinarily skilled artisan would reasonably apply Miyake’s teachings regarding a cache memory to Tamura’s buffer memory. With respect to the third contention, we disagree that the Examiner erred. As the Examiner observes (Ans. 21), Larsen notes that “the output from register 302 is denoted ‘block 1 lock control’ signal, the output from register 304 is denoted ‘block 2 lock control’ signal, and so on” (Larsen, col. 5, ll. 22–25). One of skill in the art would understand the references to specific memory blocks as teaching that the registers store addresses, and would reasonably combine that teaching with Tamura and Miyake as “an Appeal 2011-003182 Application 10/883,950 6 address register for storing the address to appoint the write-protected region of the volatile memory,” as recited in claim 1. With respect to the fourth contention, we agree with the Examiner’s findings that the state machine of Kasai “controls the operation of flash memory” and that “the state machine is a programmable device which can be programmed to transition between states to control the operation of integrated circuits” (Ans. 22). We further agree with the Examiner’s conclusion that “it would have been obvious to program the state machine to send a signal to an address register that stores the address of the block that is being protected” (id.). With respect to the fifth contention, we note that the Examiner cites additional evidence to support the assertion that it is well known in the art to include a status register to show the status of memory blocks (Ans. 23, citing US 2002/0095545 (Dalvi) and US 2002/0144066 (Talreja)). “Where a reference is relied on to support a rejection, whether or not in a ‘minor capacity,’ there would appear to be no excuse for not positively including the reference in the statement of the rejection.” In re Hoch, 428 F.2d 1341, 1342 n.3 (CCPA 1970). Nevertheless, the Examiner’s reasoning drawn from these references is sound and is unrebutted by Appellants. For these reasons, we sustain the rejection of claim 1, as well as of claims 9–11, which fall therewith. Claims 2 and 5 Appellants contend that the Examiner erred in finding that Miyake teaches “generat[ing] a flag signal that indicates whether an input address corresponds to the write-protected region,” as recited in claim 2 (Br. 8). We Appeal 2011-003182 Application 10/883,950 7 disagree. As the Examiner correctly states, Miyake teaches a control unit with a comparator that compares addresses stored in the address register in combination with generation of the lock flag (Ans. 23–24, citing Miyake, col. 11, ll. 10–67). As such, we conclude that Miyake teaches the limitation. We accordingly sustain the rejection of claim 2, as well as of claim 5, which falls therewith. Claim 3 Appellants contend that the Examiner erred in finding that Tamura teaches “control[ling] the volatile and non-volatile memories in response to the flag signal such that data stored in the volatile memory is read and stored in the non-volatile memory when the flag signal is activated,” as recited in claim 3 (Br. 8–9). Appellants’ argument mischaracterizes the basis for rejection by focusing exclusively on the Examiner’s citation of Tamura when the Examiner has, in fact, relied on the combination of Tamura and Miyake. The test for obviousness is what the combined teachings of the prior art would have suggested to the hypothetical person of ordinary skill in the art. In re Keller, 642 F.2d 413, 425 (CCPA 1981). As the Examiner notes (Ans. 24), Tamura teaches that “[t]he data which is input to the host interface circuit 40 or the data which is output from the host interface circuit 40 is temporarily held in the data buffer 4. The data which is read from the flash memories 2 and 3 or the data which will be written in the flash memories 2 and 3 is temporarily held in the data buffer 4” (Tamura, col. 7, ll. 62–67, emphases added). Since Miyake teaches controlling the volatile memory Appeal 2011-003182 Application 10/883,950 8 based on the value of the lock flag (Miyake, col. 10, ll. 19–24), we conclude that the limitation is obvious over the combination of Tamura and Miyake. Appellants’ specific contention that Tamura “teaches directly away from what is recited in Claim 3” (Br. 8–9) is unpersuasive because Tamura does not criticize, discredit, or otherwise discourage the solution of reading and storing data in the nonvolatile memory in response to a change in lock- flag value. See In re Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004). We accordingly sustain the rejection of claim 3. Claim 4 Appellants contend that the Examiner erred in finding claim 4’s limitation of “when the flag signal is activated, the at least one control circuit controls the non-volatile memory such that no read operation of the non-volatile memory is performed” obvious over the combination of cited references (Br. 9). The Examiner reasons that because Miyake teaches write-protection of volatile memory based on a lock-flag value (Miyake, col. 10, ll. 6–18) and because Kasai teaches read-protection based on the value of a “security information” indicator (Kasai, col. 2, ll. 32–41) that the limitation is obvious (Ans. 24). We agree with this reasoning since the teaching value of Kasai is read-protection based on an indicator value. Appellants’ argument that Kasai does not disclose that the security function is activated in response to a flag signal that “indicates whether the input address corresponds to the write-protected region” attacks Kasai individually when the Examiner has relied on the combination of the cited references (Br. 9). We accordingly sustain the rejection of claim 4. Appeal 2011-003182 Application 10/883,950 9 Claim 7 Appellants contend that the Examiner fails to address the specific recitations of claim 7 that “when the information stored in the status register indicates that the volatile memory is partially or wholly appointed to the write-protected region, the signal generator activates or inactivates the flag signal based on the output of the comparator” (Br. 9–10). We disagree. The Examiner makes a specific finding that Miyake teaches address comparison and generation of the lock flag based on the determined range of locked addresses (Ans. 6, 25). Since Appellants’ argument does not address these findings, we sustain the rejection of claim 7. Claim 8 Appellants contend that the Examiner fails to explain why the limitation of “when the information stored in the status register indicates that the volatile memory is not partially or wholly appointed to the write- protected region, the signal generator inactivates the flag signal irrespective of the output of the comparator,” as recited in claim 8. The Examiner finds that one of ordinary skill in the art would understand that there is no useful value in activating the lock flag when the volatile memory is not write protected (Ans. 25). Therefore, the Examiner reasons, it would have been obvious to inactivate the lock flag when the memory is not locked (Ans. 25). Appellants leave this reasoning unchallenged. We accordingly sustain the rejection of claim 8. Appeal 2011-003182 Application 10/883,950 10 Claims 12 and 20 Appellants make the following contentions with respect to the rejection of independent claim 12: 1. Appellants contend that the Examiner erred because the identified register of Chevallier is used to store a lock command that locks the nonvolatile flash memory instead of the volatile memory recited in claim 12 (Br. 11). 2. Appellants contend that the Examiner erred because Miyake fails to disclose “a control circuit that is configured to store the address appointing the locked region … in response to the control signal,” as recited in claim 12 (Br. 12). With respect to the first contention, the Examiner relies on Miyake’s teaching of locking volatile memory and Chevallier’s teaching of a lock register storing lock commands and control data words (Ans. 26, citing Chevallier ¶¶ 25, 34, 36). The relevant teaching value of Chevallier is in its disclosure of the control data word including the address of the block being protected. We conclude, in agreement with the Examiner, that one of ordinary skill in the art would understand this teaching to be relevant to Miyake’s protection of volatile memory (see Ans. 26). With respect to the second contention, we concur with the Examiner’s finding that Miyake teaches sending a cache-block lock or unlock instruction to a control unit to set a replace-inhibition state of specified cache blocks (Ans. 27, citing Miyake, col. 13, ll. 44–67; col. 27, ll. 1–24). In particular, since Miyake teaches that a signal for the lock/unlock instruction is supplied to a lock/unlock control unit that is made active when a given address region Appeal 2011-003182 Application 10/883,950 11 of the cache memory is scanned (Miyake, col. 27, ll. 14–24), we conclude that Miyake teaches the limitation. For these reasons, we sustain the rejection of claim 12, as well as of claim 20, which falls therewith. Claim 13 Appellants contend that the Examiner erred in finding it inherent among the teachings of Tamura, Miyake, and Chevallier that “when the flag signal is activated, the first memory controller makes the volatile memory perform an operation corresponding to an input command,” as recited in claim 13. Appellants’ argument that “it clearly is not inherent that the memory controller perform an operation in response to activation of the flag signal” (Br. 12, emphasis added) is incommensurate with the scope of the claim. Further, the Examiner correctly observes that the claim is silent regarding the specific nature of the operation, which can include reading data, writing data, or rejecting write data if the block is write-protected (Ans. 27). We accordingly sustain the rejection of claim 13. Claims 14–16 Appellants contend that the Examiner erred because Tamura does not disclose a state machine as recited in claim 14 and because the Examiner fails to explain why the state machine of Miyake would be used to control Tamura’s error-correction circuit (Br. 12–13). We do not find these contentions persuasive. We understand the rejection to be based on Tamura’s disclosure of the elements recited in claim Appeal 2011-003182 Application 10/883,950 12 14 in combination with Miyake’s controller, which acts as a state machine (Ans. 11–12; see also id. 9–10). We conclude that one of skill in the art would reasonably understand that the broad functionality of the controller described by Miyake could be extended to control the error correction and data input/output circuit disclosed by Tamura. We accordingly sustain the rejection of claim 14, as well as of claims 15 and 16, which fall therewith. Claims 18 and 19 Appellants contend that the Examiner provides insufficient reasoning to support the rejections of claims 18 and 19 (Br. 13). The limitations recited in those claims generally parallel the limitations recited in claims 7 and 8. For substantially the same reasons we express supra, we sustain the rejections of claims 18 and 19. Claims 26 and 27 Appellants make four contentions that generally parallel those made for claim 1 (Br. 13–14). For substantially the same reasons we express supra, we sustain the rejections of claims 26 and 27. CONCLUSION1 On the record before us, we conclude the following: 1 We have decided the appeal before us. In the event of further prosecution, we direct the Examiner’s attention to claim 26’s recitation of “the non- volatile memory” without any apparent antecedent basis. We leave it to the Examiner to determine whether that claim and those that depend therefrom satisfy the requirements of 35 U.S.C. § 112, second paragraph. Appeal 2011-003182 Application 10/883,950 13 (1) the Examiner did not err in rejecting claims 1–5, 7–11, 26, and 27 under 35 U.S.C. § 103(a) as unpatentable over Tamura, Miyake, Larsen, and Kasai; (2) the Examiner did not err in rejecting claims 12–15 and 18–20 under 35 U.S.C. § 103(a) as unpatentable over Tamura, Miyake, and Chevallier; and (3) the Examiner did not err in rejecting claim 16 under 35 U.S.C. § 103(a) as unpatentable over Tamura, Miyake, Chevallier, and Kasai. DECISION The Examiner’s decision rejecting claims 1–5, 7–16, 18–20, 26, and 27 is affirmed. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED tj Copy with citationCopy as parenthetical citation