Ex Parte Huang et al

Patent Trial and Appeal Board

Nov 21, 2013

11005137 (P.T.A.B. Nov. 21, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/005,137 12/06/2004 Yunteng Huang SIL.0022US 4686
21906 7590 11/22/2013
TROP, PRUNER & HU, P.C.
1616 S. VOSS ROAD, SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
TIMORY, KABIR A
ART UNIT PAPER NUMBER
2631
MAIL DATE DELIVERY MODE
11/22/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte YUNTENG HUANG,
SUSUMU HARA, and GARY HAMMES
____________________

Appeal 2011-006584
Application 11/005,137
Technology Center 2600
____________________

Before ST. JOHN COURTENAY III, THU A. DANG, and
CARL W. WHITEHEAD, JR., Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1-27. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

A. INVENTION
According to Appellants, the invention relates to data communication
and more particularly to acquiring data and clock signals associated with
data communication (Spec. 2, ll. 3-4).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary:
1. A method comprising:

removing a DC offset from a loop having an amplifier
coupled to receive an input signal;

applying a selected slice level to the loop; and

measuring an offset slice level at an output of the
amplifier based on the applied selected slice level.

C. REJECTION
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Rawlins U.S. 2003/0128776 A1 July 10, 2003
King U.S. 6,657,488 B1 Dec. 2, 2003
Cove U.S. 2004/0174210 A1 Sept. 9, 2004

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Claims 1-4, 7-16, and 20-22 stand rejected under 35 U.S.C. § 102(b)
as being anticipated by Rawlins.
Claims 5 and 6 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Rawlins and Cove.
Claims 17-19 and 23-27 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Rawlins and King.

II. ISSUES
The dispositive issues before us are whether the Examiner has erred in
finding that Rawlins teaches “applying a selected slice level to the loop” and
“measuring an offset slice level at an output of the amplifier based on the
applied selected slice level” (claim 1, emphasis added).

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
1. Rawlins discloses a feedback loop circuit that reduces DC
offset (Abstract), wherein Figure 52 is reproduced below:

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Figure 52 shows an open loop circuit 5200 that includes a summing
node 5202, an AGC amplifier 5222, an output node 5204, a switch 5206, and
a storage device 5208 comprising a capacitor 5210 (p. 18, [0334]).
2. Switch 5206 receives a control signal, DC voltage acquire
signal 5216, wherein when the DC voltage acquire signal 5216 is high, a
voltage at output node 5204 is stored in storage device 5208, while when the
DC voltage acquire signal 5216 is low, the storage devices 5208 holds the
stored voltage (p. 18, [0338]).

IV. ANALYSIS
Claims 1-4, 7-16, and 20-22 rejected under § 102
Although Appellants admit that Rawlins’ DC voltage acquire signal
5216 “is either at a one value or a zero value,” Appellants argue that “this is
merely a control signal that does not, by itself or via any other means, apply
a slice level to a loop …. [n]or is it a threshold voltage” (App. Br. 11).
According to Appellants, “when the DC voltage acquired is high, switch
5206 closes, and when it is low this switch opens” but “in neither event is
this signal applied to the loop itself” (id.). Appellants further contend that
“Rawlins further fails to teach measuring an offset slice level at an amplifier
output that is based on an applied selected slice level, as Rawlins is wholly
silent with regard to any type of slice information” (App. Br. 12).
However, the Examiner points to Appellants’ Specification which
defines “A slicing level is the threshold voltage at which an incoming
signal is determined to be either a ‘1’ bit or a ‘0’ bit” (Ans. 15, citing
Spec.). The Examiner then finds that “Rawlins et al. clearly shows an open
loop circuit 5200 for reducing DC offsets in a receiver channel” (Ans. 15)
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wherein the Examiner “makes his broadest reasonable interpretation in light
of the specification” that “the DC voltage acquire signal 5216 to be the
selected slice level” (Ans. 16).
The Examiner also finds that the “DC voltage acquire signal 5216…
is summed with input signal 5218… to produce[sic] a summed signal 5212”
which is then “provided to the amplifier 5222” and “[t]he DC offset
voltage… is measured at the output of the amplifier 5222 at node 5204”
(Ans. 19). That is, the Examiner finds that “at node 5204 DC offset voltage
is measured based on the amplified DC offset voltage provided by the
amplifier 5222” (id.).
We find no error with the Examiner’s findings
To determine whether Rawlins teaches “applying a selected slice level
to the loop” and “measuring an offset slice level at an output of the amplifier
based on the applied selected slice level” as recited in claim 1, we give the
claim its broadest reasonable interpretation consistent with the Specification.
See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). However, we will
not read limitations from the Specification into the claims. In re Van Geuns,
988 F.2d 1181, 1184 (Fed. Cir. 1993).
Claim 1 does not define “slice level” other than a selected slice level
is applied to the loop, and an offset slice level is measured at the amplifier’s
output based on the applied selected slice level. Thus, we give “selected
slice level” its broadest reasonable interpretation as any level/input that has
been selected to be applied to a loop. Similarly, we give “offset slice level”
its broadest reasonable interpretation as any offset level/output to be
measured at the output of the amplifier.
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Rawlins discloses a feedback loop circuit that reduces DC offset, (FF
1), wherein a switch in the loop 5200 receives a DC voltage acquire signal
5216 (FF 2). That is, Rawlins discloses applying a DC voltage acquire
signal to the switch in the loop. We find that, since the DC voltage acquire
signal is applied to the switch in the loop, the DC voltage acquire signal is
applied to the loop itself.
We also find no error in the Examiner’s finding “the DC voltage
acquire signal 5216 to be the selected slice level” (Ans. 16). As the
Examiner points out, Appellants’ Specification defines a “slicing level” as
the voltage “at which an incoming signal is determined to be either a ‘1’
bit or a ‘0’ bit” (Ans. 15). As Appellants admit, Rawlins’ “DC voltage
acquire signal 5216 ‘is either at a one value or a zero value’” (App. Br. 11).
Thus, we find no error, in view of the Examiner’s “broadest reasonable
interpretation [of the claim] in light of the specification” (Ans. 16), that
Rawlins discloses “applying a selected slice level to the loop” as required by
claim 1.
We also find no error in the Examiner’s finding that “at node 5204
DC offset voltage is measured based on the amplified DC offset voltage
provided by the amplifier 5222” (Ans. 19). Since the measured offset
voltage at the node 5204 is based on the DC voltage acquire signal 5216 (FF
2), we find that Rawlins discloses measuring the offset signal at the output
of the amplifier based on the DC voltage acquire signal. In view of the
broad but reasonable claim interpretation, we find no error with the
Examiner’s finding that Rawlins discloses “measuring an offset slice level at
an output of the amplifier based on the applied selected slice level” as
required by claim 1.
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Appellants provide no arguments with respect to claims 2 and 7-9, and
thus, claims 2 and 7-9 fall with claim 1.
As to claims 3 and 4, although Appellants argue that “[t]he only
summation performed instead in Rawlins at summer 5202 is an operation
between a receiver channel signal and a stored DC voltage output signal
5214” and thus “there is no loop offset value that is obtained from such
sum” (App. Br. 13), we find no error with the Examiner’s finding that “the
summing node 5202 receives input signal 5218 and the stored measured DC
offset voltage signal 5214 and provides a summed 5212 output signal to the
amplifier 5222” (Ans. 21).
As to claims 10 and 11, although Appellants contend that Rawlins
does not teach “inserting a selected slice level into a feedback loop while the
feedback loop is opened” (App. Br. 13), we find no error with the
Examiner’s finding that “Rawlins discloses ‘Once the DC offset voltage is
captured, the feedback loop may be opened’” (Ans. 21, emphasis omitted).
Appellants provide similar arguments for claims 12-16, and 20-22 to
those of claims 1 and 10, respectively (App. Br. 14-16), and thus, claims 12-
16 and 20-22 fall with claims 1 and 10.
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claims 1-4, 7-16, and 20-22 over Rawlins.

Claims 5, 6, 17-19, and 23-27 rejected under §103
As for claim 5, Appellants merely contend that “Cove fails to teach a
user-selected slice level” (App. Br. 16). However, we find no error with the
Examiner’s finding that “Cove et al. discloses ‘Second offset device 108
may provide a manually (interpreted to be user selected) tunable DC offset
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cancellation signal” (Ans. 25). Accordingly, we find that Appellants have
not shown that the Examiner erred in rejecting claim 5 over Rawlins in
further view of Cove.
As for claims 17-19, Appellants merely contend that “the secondary
reference fails to remedy the missing subject matter of Rawlins” and that
“there is no basis for combining these disparate references” (App. Br. 16).
As for claims 23-26, Appellants merely repeat that “there is no reason to
combine the references” (App. Br. 17).
However, as discussed above, we find no deficiencies in Rawlins.
Further, we find no error with the Examiner’s finding that the references
both “disclose a DC offset cancellation of a feedback loop system” and the
Examiner’s conclusion that “it would have been obvious… to combine [the
references] in order to yield predictable results” (Ans. 26, citing KSR Int’l
Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007)).
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claims 17-19 and 23-26 over Rawlins in further
view of King.
As for claim 27, Appellants merely repeat that “Rawlins fails to teach
the selected slice level” and add that “in Rawlins its system has an open
loop, rather than a closed loop operation” (App. Br. 17). However, as
discussed above, we find no error with the Examiner’s finding that Rawlins
discloses selecting a slice level. Further, we find no error with the
Examiner’s finding that “Rawlins et al. discloses ‘a DC offset voltage at a
particular receiver channel node may be captured and stored using a closed
feedback loop’” (Ans. 22, citing Rawlins at [0332], emphasis omitted).
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Accordingly, we also find no error in the Examiner’s rejection of
claim 27 over Rawlins in further view of King.

V. CONCLUSION AND DECISION
The Examiner’s rejections of claims 1-4, 7-16, and 20-22 under
35 U.S.C. § 102(b) and of claims 5, 6, 17-19 and 23-27 under 35 U.S.C.
§ 103(a) are affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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