Ex Parte Howard

Patent Trial and Appeal Board

Sep 27, 2018

12817839 (P.T.A.B. Sep. 27, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/817,839 06/17/2010
30955 7590
LATHROP GAGE LLP
2440 Junction Place
Suite 300
Boulder, CO 80301
10/01/2018
FIRST NAMED INVENTOR
Kevin D. Howard
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
501788 6426
EXAMINER
LINDLOF,JOHNM
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
10/01/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patent@lathropgage.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte KEVIN D. HOWARD
Appeal2018---002649
Application 12/817,839
Technology Center 2100
Before JOHN A. JEFFERY, DENISE M. POTHIER, and
NORMAN H. BEAMER, Administrative Patent Judges.
JEFFERY, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner's
decision to reject claims 1, 2, 4, 5, 7-9, and 12. Claims 3, 6, 10-12, and 13-
16 have been canceled. App. Br. 14--15. We have jurisdiction under 35
U.S.C. § 6(b ). We reverse.
STATEMENT OF THE CASE
Appellant's invention is a microprocessor system on a chip (MPSoC)
that implements parallel processing and includes plural cores, each formed
as a system on a chip (SOC). An on-chip switch fabric communicates with
1 Appellant identifies the real party in interest as Massively Parallel
Technologies, Inc. App. Br. 3.
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Application 12/817 ,839
each core to provide inter-core communication. See generally Abstract;
Spec. ,r 2. Claims 1 and 7 are illustrative:
1. A multiprocessor system on a chip (MPSoC) for implementing
parallel processing comprising:
a plurality of cores, each comprising a system on a chip, wherein each
of the cores functions as a node in a parallel processing system operating as
a structured cascade; and
an on-chip switch fabric directly connected to each of the cores;
wherein the on-chip switch fabric is configurable for coordinated
simultaneous direct communication between multiple pairs of the cores to
form the structured cascade based upon position of each of the plurality of
cores within the structured cascade, wherein, for each direct communication,
data transfer from/to each core of the pair is directly coupled in time.
7. A parallel processing system implemented as a structured cascade,
compnsmg:
a plurality of processor chips, each comprising a multiprocessor
system on a chip having a plurality of systems on a chip (SOCs ), where each
SOC is directly coupled to an on-chip switch fabric of the multiprocessor
system on a chip; and
an off-chip switch fabric communicatively coupled directly to each of
the on-chip switch fabrics of the plurality of processor chips for enabling
simultaneous directly coupled communication between multiple independent
pairs of the plurality of SOCs of different ones of the processor chips;
wherein, for each directly coupled communication, data transfer
from/to each SOC of the pair is directly coupled in time.
THE REJECTIONS
The Examiner rejected claims 1, 2, and 4 under 35 U.S.C. § 102(b) as
anticipated by Sang-II Han et al., An Efficient Scalable and Flexible Data
Transfer Architecture for Multiprocessor SoC with Massive Distributed
Memory, DAC 2004 250--55, ACM (2004) ("Han"). Final Act. 2-3. 2
2 Throughout this opinion, we refer to (1) the Final Rejection mailed October
6, 2016 ("Final Act."); (2) the Appeal Brief filed July 21, 2017 ("App. Br.");
2
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Application 12/817 ,839
The Examiner rejected claims 7-9 and 12 under 35 U.S.C. § I02(b) as
anticipated by Barroso (US 2002/0010840 Al; published Jan. 24, 2002).
Final Act. 3-5.
The Examiner rejected claim 5 under 35 U.S.C. § 103 as unpatentable
over Han and Barroso. Final Act. 5---6.
THE ANTICIPATION REJECTION OVER HAN
Regarding independent claim 1, the Examiner finds that Han
discloses, among other things, ( 1) plural "cores" (subsystems) that each
function as a node in a parallel processing system operating as a structured
cascade, and (2) an "on-chip switch fabric" ( distributed memory server
(DMS)) connected directly to each core, where the fabric is said to be
configurable for coordinated simultaneous direct communication between
multiple pairs of subsystem-based cores in Han's Figure 1. See Final Act.
2-3; Ans. 4. According to the Examiner, this coordinated simultaneous
direct communication enables forming the structured cascade based on each
core's position within the cascade as claimed because each subsystem-based
core in Han must "be in position" to receive data. Ans. 5. The Examiner
adds that, for each such direct communication, data transfer from/to each
core is directly coupled in time in view of Han's clock-based synchronous
system. Final Act. 3; Ans. 4.
Appellant argues that because Han decouples communication by
introducing a Memory Server Access Point (MSAP) between a processing
core and data bus, there is no direct communication between pairs of cores,
(3) the Examiner's Answer mailed November 16, 2017 ("Ans."); and (4) the
Reply Brief filed January 15, 2018 ("Reply Br.").
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Application 12/817 ,839
let alone that such direct communication is also simultaneous as claimed.
App. Br. 8-9; Reply Br. 6-8. Appellant adds that because Han's MSAPs (1)
decouple sending and receiving data, and (2) transfer data over a single
shared data bus, Han cannot support operating the recited structured cascade
since communication at any given time slot can only occur between a single
pair of MSAPs. App. Br. 9-10.
ISSUE
Under § 102, has the Examiner erred in rejecting claim 1 by finding
that Han discloses an on-chip switch fabric configurable for providing the
recited functionality, including coordinated simultaneous direct
communication between multiple pairs of cores?
ANALYSIS
We begin by noting that the Examiner rejects all but one claim as
anticipated by either Han or Barroso. See Final Act. 2-5. We emphasize
"anticipated" here, for it is well settled that prior art references need not be
analogous art to anticipate. See State Contracting & Eng 'g Corp. v.
Condotte Am., Inc., 346 F.3d 1057, 1068 (Fed. Cir. 2003); see also MANUAL
OF PATENT EXAMINING PROCEDURE (MPEP) § 2131.05 (9th ed. Rev.
08.2017, Jan. 2018) (citing State Contracting). Therefore, the Examiner's
statement that a prior art reference must either be in Appellant's field of
endeavor or reasonably pertinent to Appellant's problem (Ans. 3--4}-
factors that are considered for determining analogous art in obviousness
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Application 12/817 ,839
determinations3-are irrelevant to the Examiner's anticipation rejections
over the cited references. Accord Reply Br. 4 (noting this point).
Turning to the anticipation rejection over Han, a key aspect of claim 1
is the recited on-chip switch fabric and its functionality. Paragraph 21 of
Appellant's Specification defines a "switch fabric" as "a network topology
where network nodes connect with each other via one or more network
switches (particularly via crossbar-type switches)." According to the
Specification, the term "switch fabric" is used in telecommunications and
various storage-area and high-speed networks, and integrating switch fabric
306 onto MPSoC 306 in Figure 3 enables each SOC to communicate with
other SOCs through the switch fabric. Spec ,r 21.
In a telecommunications context, the term "fabric" refers to the
physical structure of a switch or network, and "[ m ]uch like a piece of cloth,
physical/logical communication channels (threads) are interwoven from
port-to-port (end-to-end)." Harry Newton, NEWTON'S TELECOM
DICTIONARY 373 (22d ed. 2006). This dictionary adds that, for switch
fabrics, ideally, data are transferred through a switch fabric on a seamless
basis. Id.
Turning to the rejection, the Examiner relies principally on the
functionality in Han's Figure 1 that illustrates a multiprocessor System on a
Chip (MPSoC) reproduced below.
3 See, e.g., In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004).
5
Appeal2018---002649
Application 12/817 ,839
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Han's MPSoC in Figure 1
As shown above, Han's MPSoC includes a DMS that the Examiner
presumably maps to the recited switch fabric. See Final Act. 3. The DMS is
connected subsystems "O," "k," and "n" that the Examiner presumably maps
to the recited "cores." See Final Act. 2. Accord Reply Br. 8 (referring to
Han's subsystems as exemplary cores). As shown in Han's Figure 1, each
subsystem is connected to an associated MSAP in the DMS that enables
transferring data between subsystems. See Han 251 § 3.
Han's Figure 2, reproduced below, shows the MSAP's basic functions
that include (1) a Local Request Acceptor (LRA); (2) a Remote Request
Acceptor (RRA); (3) Memory Scheduler (MS); (4) Memory Activator (MA);
and ( 5) Wrappers.
6
Appeal2018---002649
Application 12/817 ,839
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As Han explains, the MSAP 's functions include, among other things,
(1) accepting local and remote data transfer requests, (2) scheduling those
requests, and (3) executing read or write requests selected by the memory
scheduler. Han 251-52 § 4. These functions are further detailed in Han's
section 4.1 and Figure 3 that, as shown below, details the MSAP's
architecture.
7
Appeal2018---002649
Application 12/817 ,839
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Han's Figure 3 showing the MSAP's detailed architecture
Given this functionality, we agree with Appellant that Han's DMS,
which the Examiner presumably maps to the recited switch fabric, is not
necessarily configurable for coordinated direct communication, let alone that
such communication is also simultaneous as claimed. As Appellant
explains, the DMS' MSAPs are intervening components between the
subsystems that provide various independent functions beyond switching,
including buffering data and scheduling received requests. See App. Br. 8-
9; see also Reply Br. 7-8; Han 251-52 §§ 4--4.1. In short, these functions
go well beyond those of the recited switch fabric that, as noted above,
switches the nodes to enable their simultaneous communication with each
other, and, notably, does so seamlessly. See NEWTON'S TELECOM
DICTIONARY at 373. That is not the case in Han where the intervening
MSAPs essentially decouple the data bus from the subsystems and
8
Appeal2018---002649
Application 12/817 ,839
introduce, among other things, buffering and scheduling functions as
Appellant indicates. See App. Br. 8; Reply Br. 7-8.
To be sure, Han's subsystems are connected to each other only via the
DMS in Figure 1 and, therefore, communicate with the DMS directly. But to
say that Han's subsystem-based cores communicate directly with each other
as the Examiner seems to suggest strains reasonable limits on this record
given the functionality of the DMS' intervening MSAPs noted above. See
Ans. 4 (finding that communication is direct from one core to another
through Han's DMS). Although communication between nodes in
Appellant's invention is via the switch fabric in Appellant's Figures 3 to 6B,
Han's intervening MSAPs perform functions markedly different from
Appellant's switch fabric, including buffering and arbitrating data transfers
over the data bus that effectively decouple the bus from the subsystems as
Appellant indicates. 4 See App. Br. 8; Reply Br. 7-8.
Therefore, we agree with Appellant that Han's DMS is not
configurable for coordinated direct communication, let alone simultaneous
direct communication between multiple pairs of cores, as claimed. Our
emphasis underscores two additional flaws in the Examiner's findings,
namely that Han's coordinated communication between subsystems is also
necessarily simultaneous and between multiple pairs of cores. See Final
Act. 3; Ans. 4--5. As Appellant indicates (Reply Br. 7), the Examiner's
reliance on Han's clocked network for teaching simultaneous
4 That Barroso' s Figure 3 shows a switch fabric 152 that is separate from
arbiter 154 is telling in this regard, at least with respect to the art-recognized
segregation of a switch fabric's functions from other distinct functions, such
as arbitration, that are performed by other components.
9
Appeal2018---002649
Application 12/817 ,839
communication between multiple pairs of cores (Ans. 4) is problematic, for
this clocked communication, at best, teaches communication between single
pairs of MSAPs serially in different time blocks-not between multiple
MSAP pairs simultaneously. See Reply Br. 7.
The Examiner's reliance on Han's parallel execution of computation
and communication via the MSAP (see Ans. 4) fares no better in this regard.
Merely because Han's MSAP allows parallel execution of computation and
communication in column 2 of page 251 does not mean that communication
between multiple pairs of subsystems necessarily occurs in parallel or is
otherwise simultaneous as the Examiner seems to suggest. See Ans. 4
(finding that communication to and from Han's cores "occurs in parallel").
Rather, Han's system merely allows communication to occur in parallel with
computation as Appellant indicates. Reply Br. 7.
So even assuming, without deciding, that Han's DMS can somehow
be considered a "switch fabric," it is not necessarily configurable for
providing coordinated simultaneous direct communication between multiple
pairs of cores, as claimed.
Therefore, we are persuaded that the Examiner erred in rejecting
independent claim 1, and dependent claims 2 and 4 for similar reasons.
Because this issue is dispositive regarding our reversing the Examiner's
rejection of these claims, we need not address Appellant's other associated
arguments.
THE ANTICIPATION REJECTION OVER BARROSO
Regarding independent claim 7, the Examiner finds that Barroso
teaches a parallel processing system implemented as a structured cascade
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Appeal2018---002649
Application 12/817 ,839
including, among other things, processor chips each with a MPSoC with
SOCs, and an off-chip switch fabric (interconnect 134) communicatively
coupled directly to each chip's on-chip switch fabric for enabling
simultaneous directly-coupled communication between multiple independent
pairs of SOCs of different chips, where, for each directly-coupled
communication, data transfer from/to each SOC of the pair is directly
coupled in time. Final Act. 3--4; Ans. 5.
Appellant argues that Barroso does not teach an off-chip switch fabric
coupled directly to each on-chip switch fabric, let alone an off-chip switch
fabric enabling simultaneously directly-coupled communication between
multiple independent pairs of SOCs of different chips as claimed. App. Br.
10-11; Reply Br. 8-11.
ISSUE
Under § 102, has the Examiner erred in rejecting claim 7 by finding
that Barroso discloses an off-chip switch fabric communicatively coupled
directly to each processor chip's on-chip switch fabric for enabling
simultaneous directly-coupled communication between multiple independent
pairs of SOCs of different chips?
ANALYSIS
Claim 7 recites, in pertinent part, that an off-chip switch fabric is
communicatively coupled directly to each chip's on-chip switch fabric. In
the rejection, the Examiner presumably maps the recited off-chip switch
fabric to interconnect 134 in Barroso's Figure 1. See Final Act. 4. Barroso's
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Appeal2018---002649
Application 12/817 ,839
Figure 1, reproduced below, shows a multiprocessor system that
interconnects nodes 102 and 104, where one node 102 is shown in detail.
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As shown above, node 102 includes Intra-Chip Switch (ICS) 112 that,
notably, includes Switch Fabric 152 as shown in Barroso's Figure 3
reproduced below.
12
Appeal2018---002649
Application 12/817 ,839
Barroso's Figure 3 showing the ICS' Switch Fabric 152
As shown in these figures, various components are located between
interconnect 134 and switch fabric 152. So even assuming, without
deciding, that Barroso's interconnect 134 is an "off-chip switch fabric" as
the Examiner seemingly suggests, it is not communicatively coupled directly
to each chip's on-chip switch fabric 152, but rather is so coupled indirectly,
namely via intervening components including router 126, input queue 128,
packet switch 132, remote protocol engine 124, and system control module
136. See Barroso ,r,r 41--43, 51-54; Figs. 1-3. Accord Reply Br. 11 (noting
this indirect connection).
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Application 12/817 ,839
For this reason alone, the Examiner's anticipation rejection of claim 7
is problematic. Nor do we find that Barroso's interconnect 134, which is
presumably the off-chip switch fabric under the Examiner's mapping, also
necessarily enables simultaneous communication between multiple pairs of
SOCs of different chips as claimed. The Examiner's reliance on the
functionality of Barroso's paragraph 53 for ostensibly teaching parallel
communication between SOCs (Ans. 5) is unavailing. As Appellant
indicates, this functionality pertains to the ICS 112 and associated interface
and buffers which are on-chip components and are, therefore, irrelevant to
the recited functionality of the off-chip switch fabric.
So leaving aside Barroso' s lacking direct coupling between off- and
on-chip switch fabrics, the Examiner has also not shown that Barroso
necessarily also teaches that such a coupling enables simultaneous directly-
coupled communication between multiple independent pairs of SOCs of
different chips for the reasons noted above and by Appellant. See App. Br.
10-11; Reply Br. 8-11.
Therefore, we are persuaded that the Examiner erred in rejecting (1)
independent claim 7, and dependent claims 8, 9, and 12 for similar reasons.
THE OBVIOUSNESS REJECTION
Because the Examiner has not shown that Barroso cures Han's above-
noted deficiencies regarding the rejection of independent claim 1, we will
not sustain the obviousness rejection of dependent claim 5 (Final Act. 5---6)
for similar reasons. We, therefore, need not address Appellant's arguments
regarding the references' combinability. See App. Br. 11-12.
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Application 12/817 ,839
CONCLUSION
The Examiner erred in rejecting (1) claims 1, 2, 4, 7-9, and 12 under
§ 102, and (2) claim 5 under § 103.
DECISION
We reverse the Examiner's decision to reject claims 1, 2, 4, 5, 7-9,
and 12.
REVERSED
15