Ex Parte Hofmann et al

Patent Trial and Appeal Board

Feb 28, 2014

11253307 (P.T.A.B. Feb. 28, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte RICHARD GERARD HOFMANN,
THOMAS ANDREW SARTORIUS, THOMAS PHILIP SPEIER,
JAYA PRAKASH SUBRAMANIAM GANASAN,
JAMES NORRIS DIEFFENDERFER, and JAMES EDWARD SULLIVAN
____________

Appeal 2011-006742
Application 11/253,307
Technology Center 2100
____________

Before JEAN R. HOMERE, JOHN A. EVANS, and PETER P. CHEN,
Administrative Patent Judges.

EVANS, Administrative Patent Judge.

DECISION ON APPEAL
Appellants1 seek our review under 35 U.S.C. § 134(a) of the
Examiner’s final rejection of Claims 1-202 as anticipated and obvious. We
have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.3

1 The Real Party in Interest is QUALCOMM Incorporated.
2 App. Br. 7.
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2

STATEMENT OF THE CASE
The claims relate to a method and apparatus for enforcing strongly-
ordered requests in a weakly-ordered processing system. See generally
Abstract.
Claims 1, 9, 10, and 15 are independent. An understanding of the
invention can be derived from a reading of exemplary Claim 1, which is
reproduced below with disputed limitations italicized:
1. A weakly-ordered processing system, comprising:
a plurality of memory devices;
a plurality of processors, each of the processors
configured to generate memory access requests to one or more
of the memory devices, each of the memory access requests
having an attribute that can be asserted to indicate a strongly-
ordered request; and
a bus interconnect configured to interface the processors
to the memory devices, the bus interconnect being further
configured to enforce ordering constraints on the memory
access requests based on the attributes.
References
The Examiner relies upon the prior art as follows:
Merchant US 5,893,151 Apr. 6, 1999
Dunshea US 2006/0155936 A1 Filed Dec. 7, 2004

3 Our decision refers to Appellants’ Appeal Brief filed July 26, 2010 (“App.
Br.”); Reply Brief filed December 23, 2010 (“Reply Br.”); Examiner’s
Answer mailed October 26, 2010 (“Ans.”); Final Office Action mailed
February 22, 2010 (“Final Rej.”); and the original Specification filed
October 19, 2005 (“Spec.”).
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The claims stand rejected as follows:4
1. Claims 1, 9, 10, and 15 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Merchant. Ans. 3-4.
2. Claims 2-8, 11-14, and 16-20 stand rejected under 35 U.S.C. § 103(a)
as obvious over Merchant and Dunshea. Ans. 4-9.

APPELLANTS’ CONTENTIONS
Anticipation
1. Merchant’s “strongly-ordered queuing structure” cannot anticipate the
claimed “weakly-ordered processing system.” App. Br. 9.
2. Merchant fails to disclose “memory access requests having an
attribute that can be asserted to indicate a strongly-ordered request.”
App. Br. 9-10 (emphasis omitted).
3. Merchant fails to disclose “a bus interconnect configured to interface
the processors to the memory devices, the bus interconnect being
further configured to enforce ordering constraints on the memory
access requests based on the attributes.” App. Br. 10 (emphases
omitted).
Obviousness
4. Dunshea fails to teach “sending a memory barrier to each of the other
memory devices accessible to the originating processor,” as recited in
Claim 2. App. Br. 13.

4 Based on Appellants’ arguments in the Appeal Brief, we will decide the
appeal on the basis of claims as set forth below. See 37 C.F.R. §
41.37(c)(1)(vii).
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Application 11/253,307

4
ISSUES ON APPEAL
Based on Appellants’ arguments in the Appeal Brief (App. Br. 7-15)
and Reply Brief (Reply Br. 2-5), the issue presented on appeal is whether the
Examiner erred in finding that Merchant discloses a “weakly-ordered
processing system.”5

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We agree with Appellants’
conclusions.

ANTICIPATION
INDEPENDENT CLAIMS 1, 9, 10, AND 15
Weakly-ordered processing system
Appellants argue independent Claims 1, 9, 10, and 15 as a group.
App. Br. 9.
Appellants contend that Merchant’s “strongly-ordered queuing
structure” cannot anticipate the claimed “weakly-ordered processing
system.” App. Br. 9.6

5 Appellants’ arguments raise additional issues. However, because we are
persuaded of error with regard to the identified issue, which is dispositive of
the rejection over Merchant, we do not reach the additional issues.
6 The recitation “weakly-ordered processing system” occurs in the preamble
of Claim 1. However, “[w]here a patentee uses the claim preamble to recite
structural limitations of his claimed invention, the PTO and courts give
effect to that usage.” Rowe v. Dror, 112 F.3d 473, 478 (Fed. Cir. 1997)
(citing Bell Commc’ns Research, Inc. v. Vitalink Commc’ns Corp., 55 F.3d
615, 620 (Fed. Cir. 1995)). The Examiner has not found that Appellants
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The Examiner finds that Merchant discloses a processing system
comprising a plurality of processors, each of which is configured to generate
memory access requests to one or more memory devices where each request
has an attribute bit that can be asserted to indicate strong- or weak-ordering.
Ans. 3-4.
Appellants contend that Merchant discloses “an apparatus for
maintaining cache coherency for snoop operations.” App. Br. 7. The
apparatus includes a “snoop queue 408” that “maintains strict bus ordering
such that all snoop requests are initiated in the same order in which they
entered the snoop queue.” Id. Accordingly, Appellants contend that
Merchant’s snoop queue is strongly-ordered. Id. (citing Merchant, col. 8, ll.
11-15). Appellants contend that Merchant allows his snoop queue to perform
read and write operations using either a weak- or strong-ordering dependent
upon the addresses of the reads and writes, wherein strong-ordering is
performed by using block bits to prevent initiation of a new operation until a
previous operation has completed, and weak-ordering may be performed by
using sleep bits to prevent initiation of a new operation until a previous
operation has been initiated. Accordingly, Appellants contend that Merchant
discloses a strongly-ordered queue structure which may be configured to
allow strong-ordering or weak-ordering of requests stored in the queue,
based on the addresses to which the requests are directed . App. Br. 7-8.
The Examiner finds that Merchant (col. 16, ll. 11-21) teaches a
“strong” ordering that is performed using block bits and a “weak” ordering

have “define[d] a structurally complete invention in the claim body and
use[d] the preamble only to state a purpose or intended use for the
invention.” Id.
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that is performed using sleep bits; the address values, or the tokens
associated with them, may then be viewed as attributes, some of which cause
block bits to be asserted and some that cause sleep bits to be asserted, thus
constituting a weakly-ordered system due to its dependency on individual
addresses rather than on policies. Ans. 11.
We agree with Appellants. Claim 1 recites a “weakly-ordered
processing system, comprising . . . a plurality of processors, each of the
processors configured to generate memory access requests.” Appellants
disclose that “[p]rocessing systems that are allowed to reorder memory
operations are generally referred to as ‘weakly-ordered’ processing
systems.” Spec. ¶ 0003. Appellants also disclose that “[a] ‘strongly-ordered’
request refers to a memory access request that cannot be executed out of
order.” Spec. ¶ 0022. The portion of Merchant relied upon to teach “weak
ordering” does not relate to a memory access request. Rather, the citation
relates to pending read and writes: “[a]dditionally, the queue structure need
not be limited to keeping track of snoop requests. For example, the queue
could be used to maintain entries corresponding to pending reads and
writes.” Merchant, col. 16, ll. 10-13. Moreover, even where Merchant’s
snoop queue relates to pending read and write entries, a strict chronological
ordering is maintained:
[a] “strong” ordering and a “weak” ordering may be allowed
dependent upon the addresses of the reads and writes, wherein
the “strong” ordering is performed by using the block bits to
prevent initiation of a new operation until a previous operation
has completed, and the “weak” ordering is performed by using
the sleep bits to prevent initiation of a new operation until a
previous operation has been initiated.
Merchant, col. 16, ll. 14-21.
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Claim terms are given their broadest reasonable construction
consistent with the specification. In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d
1359, 1369 (Fed. Cir. 2004). Nonetheless, we are not persuaded that
Merchant’s “entries corresponding to pending reads and writes” are the
equivalent of the claimed “memory access requests.”
We agree with the Examiner’s finding that Merchant discloses a
processing system comprising a plurality of processors, each of which is
configured to generate memory access requests to one or more memory
devices where each request has an attribute bit that can be asserted to
indicate strong- or weak-ordering. Ans. 3-4. However, for the reasons
discussed above, we find that the configuration of the processors does not
conform Merchant to a “weakly-ordered processing system,” as recited in
Claim 1. Notwithstanding the memory requests that Merchant’s processors
may be configured to generate, Merchant includes a “snoop queue 408” that
“maintains strict bus ordering such that all snoop requests are initiated in the
same order in which they entered the snoop queue.” App. Br. 7. (citing
Merchant, col. 8, ll. 11-15).
Memory access requests having an attribute that can be
asserted to indicate a strongly-ordered request
Appellants contend that Merchant teaches that a “strong” or “weak”
ordering may be allowed depending upon the addresses of the reads and
writes. But, Appellants contend, an ordering based on an address of a
memory access request does not read on “the memory access requests
having an attribute that can be asserted to indicate a strongly-ordered
request,” as recited in Claim 1. App. Br. 9.
The Examiner finds that Merchant teaches “a ‘strong’ ordering that is
performed using block bits and a ‘weak’ ordering that is performed using
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sleep bits; the block bits may then be viewed as attributes, some of which
indicate a ‘strong’ ordering and thus cause block bits to be asserted.”
Ans. 11.
Appellants contend that “block bits” and “sleep bits” are merely logic
employed in Merchant’s queuing structure to perform ordering. The block
bits and sleep bits are not attributes of the memory access requests. App. Br.
10; Reply Br. 4.
We agree with Appellants. Merchant discloses that each entry into the
snoop queue comprises an address and a plurality of logic bits, including
“block bits” and “sleep bits.” See col. 8, ll. 16-25; Table 1.
In view of the foregoing, we decline to sustain the rejection of Claims
1, 9, 10, and 15 as anticipated.7

OBVIOUSNESS
DEPENDENT CLAIMS 2-8, 11-14, AND 16-20
Weakly-ordered processing system
Appellants argue dependent Claims 2-8, 11-14, and 16-20 as a group.
App. Br. 13. Appellants contend that Dunshea fails to cure the deficiencies
of Merchant discussed above. The Examiner does not apply Dunshea to the
limitations argued above. Ans. 12-13.
For the reasons discussed above, we decline to sustain the rejection of
Claims 2-8, 11-14, and 16-20.

7 Appellants’ arguments raise additional issues. However, because we are
persuaded of error with regard to the identified issue, which is dispositive of
the rejection over Merchant, we do not reach the additional issues.
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ORDER
The rejection of Claims 1, 9, 10, and 15 under 35 U.S.C. § 102 is
REVERSED.
The rejection of Claims 2-8, 11-14, and 16-20 under 35 U.S.C. § 103
is REVERSED.

REVERSED

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