Ex Parte Hobson

Patent Trial and Appeal Board

Mar 30, 2016

12910483 (P.T.A.B. Mar. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/910,483 10/22/2010
22879 7590 04/01/2016
HP Inc.
3390 E. Harmony Road
Mail Stop 35
FORT COLLINS, CO 80528-9544
FIRST NAMED INVENTOR
Louis B. Hobson
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
82265198 8226
EXAMINER
MISIURA, BRIAN THOMAS
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
04/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
ipa.mail@hp.com
barbl@hp.com
yvonne.bailey@hp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LOUIS B. HOBSON
Appeal2014-004053
Application 12/910,483
Technology Center 2100
Before JOHN A. EVANS, MATTHEW R. CLEMENTS, and
SCOTT E. BAIN, Administrative Patent Judges.
BAIN, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner's
final rejection of claims 1-10 and 12-15. We have jurisdiction under
35 U.S.C. § 6(b).
We affirm-in-part.
STATEMENT OF THE CASE
Appellant's invention relates to power management in computing
machines, and in particular to storing and retrieving the process state during
transition between sleep state and other states. Spec. i-f 1. Claims 1 and 8
1 Appellant identifies Hewlett-Packard Development Company, LP and
Hewlett-Packard Company as the real parties in interest. App. Br. 2.
Appeal2014-004053
Application 12/910,483
are illustrative of the invention, and read as follows (with the disputed
limitations in italics):
1. A method for managing a computing machine comprising:
powering a memory to retain a process state of the
computing machine if the computing machine is in a sleep state,
the sleep state comprising an S3 sleep state according to
Advanced Configuration and Power Interface (ACPI)
specifications; and
transferring the process state from the memory to a non-
volatile storage device;
wherein the computing machine remains in the S3 sleep
state as the process state is transferred from the memory to the
non-volatile storage device.
8. A computing machine comprising:
a memory to retain a process state of the computing
machine if the computing machine is in a sleep state; and
a non-volatile storage device to receive and store the
process state from the memory; and
a controller to transfer the process state from the memory
to the non-volatile storage device after a predefined period of
time if the computing machine remains in the sleep state;
wherein the controller transfers the process state of the
computing machine from the non-volatile storage device to the
memory when the computing machine enters a power on state,
the BIOS of the computing machine not being loaded when
resuming to the power on state.
App. Br. 19-20 (emphasis added).
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Application 12/910,483
PRIOR ART
The Examiner relies upon the following prior art in rejecting the
claims:
Hane butte
Cantwell
Nanbu
US 7 ,594,073 B2
US 2008/0126815 Al
US 2010/0318817 Al
THE REJECTIONS ON APPEAL
Sept. 22, 2009
May 29, 2008
Dec. 16, 2010
Claims 1-3 and 5 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Cantwell. Ans. 2--4.
Claims 1and5-7 stand rejected under 35 U.S.C. § 102(e) as
anticipated by Nanbu. Ans. 5---6.
Claims 1, 3, and 4 stand rejected under 35 U.S.C. § 102(b) as
anticipated by Hanebutte. Ans. 4--5.
Claims 8-10 and 12-15 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Hane butte and Cantwell. Ans. 7-9. 2
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments presented in this appeal. Any other arguments Appellant could
have made but chose not to make in the Briefs are deemed waived. See
37 C.F.R. § 41.37(c)(l)(iv). With respect to the anticipation rejections based
2 Appellant also argues the Examiner erred in objecting to claim 8, and
requests we not sustain the objection. App. Br. 9. Objections, however, are
reviewable only by petition to the Director, 3 7 C.F .R. § § 1.113 (a), 1.181, so
we do not address or disturb the objection to claim 8. The remaining claims
16 and 17 have been allowed; claim 11 is objected to as depending from a
rejected base claim but allowable if rewritten in independent form; and
claims 18-20 were canceled. Final Act. 9; App. Br. 4, 22.
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Application 12/910,483
upon Cantwell (claims 1-3 and 5) and the anticipation rejections based upon
Nanbu (claims 1 and 5-7), we agree with the Examiner's findings and
conclusions and adopt them as our own. With respect to the remaining
rejections, however, we are persuaded by Appellant's arguments that the
Examiner erred. We provide the following to highlight and address specific
arguments.
Rejection of Claims 1-3 and 5 as Anticipated by Cantwell
Appellant contends that Cantwell fails to disclose a computing
machine "remain[ing] in the S3 sleep state as the process state is transferred"
from memory (such as RAM) to non-volatile storage device (such as hard
drive), as required in claim 1 and its dependent claims 2, 3, and 5. App. Br.
10-11. Although Appellant admits that Cantwell discloses a machine that
can be in an S3 (sleep) state or in an S4 (hibernate) state, as cited by the
Examiner, Final Act. 2-3, Appellant argues that Cantwell "merely describes
what these states do" individually but does not teach remaining in the S3
sleep state "as the process state is transferred." Id. at 10; Reply Br. 5.
The Examiner answers that Cantwell not only discloses the S3 and S4
states individually, but also discloses a "transition" directly between S3 and
S4 states. Ans. 10. During that transition, the Examiner explains, "contents
[including process state] of the RAM are transferred from the RAM
[memory] to the hard disk [non-volatile storage device]." Id.; see also
Cantwell i-fi-15, 18. Moreover, in Cantwell, the RAM remains powered "as"
the process state is transferred, which means, according to the Examiner, the
machine "is considered to 'remain in the S3 sleep state ... "' as claim 1
recites. Id. (emphasis added). We agree.
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Application 12/910,483
Cantwell discloses the S3 state (a standard defined under the
Advanced Configuration and Power Interface (ACPI) specification), in
which "operating system recovery information is stored in RAM," RAM
remains powered, and various processing components are powered off. See
Cantwell i-f 18; see also id. i-f 5 (describing information stored in RAM in S3
state). 3 Cantwell further discloses that to save "additional power," the
machine may enter the "S4 hibernate mode" by "storing RAM information
in persistent [non-volatile] memory, such as a hard disk drive, and then
powering down the RAM and other components powered in the S3 mode."
Cantwell i-f 5 (emphasis added); Ans. 10.
The italicized phrase "then powering down the RAM and other
components powered in the S3 mode" signifies a sequence in which the
machine powers down RAM (therefore leaving S3 state) only after the
information in RAM (process state) is stored on the hard disk drive. See id.
Thus, we find that Cantwell discloses a machine that remains in S3 sleep
state "as" information (process state) is transferred from RAM (memory) to
hard disk (non-volatile storage). Id. 4
Therefore, the Examiner did not err in finding Cantwell to disclose a
machine that "remains in the S3 sleep state as the process state is
3 Appellant does not dispute the Examiner's finding that Cantwell's
disclosure of information in RAM, such as operating system recovery
information, encompasses Appellant's "process state." Final Act 2-3; Spec.
i-f 15 (defining process state as including "information, data, and/ or
configuration settings" loaded into memory).
4 Paragraph 6 of Cantwell (not cited by the Examiner), which discloses
"cascading systems" that "transition" from the "S3 reduced power state to
the S4 reduced power state," is consistent with and further supports this
finding.
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Application 12/910,483
transferred from the memory to the non-volatile storage device," as claim 1
recites. App. Br. 19 (emphasis added). Appellant argues no other claim
limitations, and does not argue dependent claims 2, 3, and 5 separately under
this rejection. Accordingly, we sustain the rejection of claims 1-3 and 5
under 35 U.S.C. § 102(b) as anticipated by Cantwell.
Rejection of Claims 1and5-7 as Anticipated by Nanbu
Appellant presents a nearly identical argument regarding the
rejections under Nanbu as it did regarding the rejections under Cantwell,
discussed above. Specifically, Appellant argues that Nanbu fails to disclose
a machine that "remains in the S3 sleep state as the process state is
transferred," and instead merely discloses the S3 and S4 states in isolation.
App. Br. 13-15. We find Appellant's argument unpersuasive for reasons
similar to those cited in our discussion of Cantwell.
As the Examiner explains in the Answer, Nanbu discloses not only the
S3 and S4 states, but also "transitioning between ... states S3 and S4."
Ans. 11 (emphasis added) (citing Nanbu Fig. 4, i-fi-17, 8). Figure 4 ofNanbu
is reproduced below:
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FIG.4
Figure 4 is a flow diagram depicting the Nanbu system state
transitions, and illustrates a transition directly from S3 ("standy mode," i.e.,
sleep) to S4 ("hibernation mode"). See also Nanbu i-fi-148, 55 (computer
changes from "standby mode (S3)" to "hibernation mode (S4)"). In S3 state,
Nanbu recites, "memory is supplied with power to hold the contents" of the
memory, and in S4 state "the PC is powered off after data on the [] memory
are copied to a secondary storage device such as a hard disk drive." Id. i-fi-1 7,
8 (emphasis added); Final Act. 5---6. Thus, Nanbu, like Cantwell, discloses a
sequence in which process state is transferred from memory to non-volatile
storage and then the PC (including RAM) is powered off, thereby leaving S3
state. See id. "As" this transition occurs, the system remains in S3 state.
See id.
The Examiner, therefore, did not err in finding Nanbu discloses
"remain[ing] in the S3 sleep state as the process state is transferred" from
memory to non-volatile storage, as claim 1 recites. Appellant does not argue
dependent claims 5-7 separately under this rejection. Accordingly, we
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sustain the rejection of claims 1and5-7 under 35 U.S.C. § 102(e) as
anticipated by N anbu.
Rejection of Claims 1, 3, and 4 as Anticipated by Hanebutte
Appellant challenges the rejections under Hanebutte on the same
grounds as the Cantwell and Nanbu rejections, namely, that Hanebutte fails
to disclose a machine that "remains in the S3 sleep state as the process state
is transferred from the memory to the non-volatile storage" but instead
merely discloses the S3 and S4 states in isolation. App. Br. 11-13. Here,
we agree with Appellant.
The Examiner asserts that Hanebutte discloses the disputed limitation
in "Column 4 lines 26-31, Figure 3A." Final Act. 4 (emphasis omitted);
Answer 4. Figure 3A ofHanebutte is reproduced below:
Figure 3A is a block diagram depicting a "system entering ACPI S4 state,"
including non-volatile cache 320, system RAM 150, and hard disk drive
(HDD) 190. According to Hanebutte, when the system enters S4 as depicted
in Figure 3A, "the OS directs that an image data for memory 150 be
generated and written to HDD 190" but the request is "intercepted and the
memory image is directed to NV cache 320." Hanebutte col. 4, 11. 26-31.
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Unlike Cantwell's and Nanbu's disclosures of state transitions from
S3 to S4, however, Hanebutte's transition to S4 cited by the Examiner is not
identified as coming from the S3 state. Rather, Hanebutte discloses "[t]he
system may be put into either S3 (sleep) state or S4 (hibernation) state
manually or automatically after a certain period of inactivity." Hanebutte
col. 3, 11. 52-54 (emphasis added); App. Br. 12. Thus, the disclosures in
Hanebutte cited by the Examiner, see Final Act. 4, Ans. 4--5, reflect
transition directly from working state to one of the power-saving modes S3
or S4, not transitioningfrom S3 to S4.
The Examiner asserts in the Answer that "transition between state S3
and S4 requires the RAM to remain powered (i.e., remain in S3 state) until
its contents are stored in the non-volatile storage device and S4 may be
entered." Ans. 11. While the accuracy of this statement does not appear to
be in dispute, the Examiner fails to cite any disclosure in Hanebutte of such
a transition from state S3 to S4. See, e.g., In re Schreiber, 128 F.3d 1473,
1477 (Fed. Cir. 1997) (anticipating reference "must disclose every limitation
of the claimed invention").
For the foregoing reasons, we do not sustain the rejection of claim 1
and its dependent claims 3 and 4 under 35 U.S.C. § 102(b) as anticipated by
Hane butte.
Rejection of Claims 8-10 and 12-15 as
Unpatentable over Hanebutte and Cantwell
Claim 8 and its dependent claims are directed to a computing machine
entering and then recovering from a power save mode. App. Br. 20.
Appellant argues that the prior art fails to teach "the BIOS of the computing
machine not being loaded" when resuming to power on state, as recited in
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claim 8. App. Br. 15-17. The Examiner relies solely upon Hanebutte as
teaching this element, citing Hane butte's disclosure that "restoring the
memory content [when resuming power on] using the NV cache may be
performed ... in an OS transparent manner." Hane butte col. 6, 11. 1---6
( emphasis added); Ans. 7. Appellant responds that "OS transparent manner"
does not mean (or teach) "without loading the BIOS," as the Examiner
assumes. App. Br. 16; Reply Br. 9. On this record, Appellant persuades us
that the Examiner has erred.
Hane butte describes, in column 5 of its Specification, resuming to
power on state from a hibernation state. The use of BIOS is prevalent
throughout this description. See Hanebutte col. 5, 11. 20-24 ("OS second
level loader works with BIOS/Option Rom 455 to decide what needs to be
run ... before a system can return what it left off when it resumes" from
power save mode), col. 5, 11. 42--43 ("When a system is booting up or
resuming" from hibernation state, for example, "the BIOS calls code stored
in the Option ROM."), col. 5, 11. 32-33 ("BIOS/Option ROM [] helps
determine what a system can do before the OS is up and running."). The
foregoing disclosures are inconsistent with the Examiner's finding that,
when Hanebutte subsequently refers to resuming to power on in an "OS
transparent manner," see supra, it means "without loading the BIOS."
Moreover, Hanebutte's reference to "OS transparent manner" cited by
the Examiner (id. at col. 6, 11. 1---6; Ans. 11) is immediately followed by the
explanation "[f]or example ... restoring the memory content from the NV
cache may be done by code in the Option ROM." Id. at col. 6, 11. 7-8
(emphasis added); Reply Br. 9. "Option ROM" is disclosed in Hane butte as
operating significantly in tandem with BIOS. See supra (preceding
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paragraph). Hane butte provides still further explanation of "restoring the
memory ... in an OS transparent manner" (id. at col. 6, 11. 11-20) and again
makes no mention of avoiding the BIOS. App. Br. 16.
In light of the foregoing, we do not find sufficient support in
Hane butte for the Examiner's finding that "restoring memory content ... in
an OS transparent manner" refers to the BIOS. The Examiner argues that,
notwithstanding the absence of an express explanation in the reference, one
of ordinary skill would understand "[t]he role of BIOS is to load an
operating system." Ans. 11-12. Reciting the role of BIOS, however, still
fails to explain how the disclosure of "OS transparent" teaches not loading
the BIOS and OS, as opposed to referring to transparency of the operation.
See Reply Br. 9-10.
On the record before us, we conclude the Examiner erred in finding
that Hane butte teaches "BIOS of the computing machine not being loaded"
as required in claim 8 and its dependent claims. We do not, therefore,
sustain the Examiner's rejection of claims 8-10 and 12-15 under 35 U.S.C.
§ 103(a) as unpatentable over Hanebutte and Cantwell.
DECISION
We affirm the Examiner's decision rejecting claims 1-3 and 5-7, but
reverse the decision rejecting claims 4, 8-10, and 12-15.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l). See 37 C.F.R.
§ 1.136(a)(l)(iv) (2013).
AFFIRMED-IN-PART
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