Ex Parte HERRELL et al

Patent Trials and Appeals Board

Apr 5, 2019

14780389 - (D) (P.T.A.B. Apr. 5, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
14/780,389 09/25/2015 Russ W. HERRELL
56436 7590 04/09/2019
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
90028910 7270
EXAMINER
THAI,TUANV
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
04/09/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
hpe.ip.mail@hpe.com
chris.mania@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte RUSS W. HERRELL, GARY GOSTIN,
GREGG B. LESARTRE, and DALE C. MORRIS 1
Appeal 2018-007568
Application 14/780,389
Technology Center 2100
Before CAROLYN D. THOMAS, JOSEPH P. LENTIVECH, and
SCOTT RAEVSKY, Administrative Patent Judges.
RAEVSKY, Administrative Patent Judge.
DECISION ON APPEAL
Appellants seek our review under 35 U.S.C. § 134(a) of the
Examiner's Final Rejection of claims 1 and 3-15, all the pending claims in
the present application (see Claims Appendix). We have jurisdiction over
the appeal under 35 U.S.C. § 6(b ).
We AFFIRM-IN-PART.
1 Appellants name Hewlett Packard Enterprise Development LP as the real
party in interest (App. Br. 1 ).
Appeal 2018-007568
Application 14/780,389
STATEMENT OF THE CASE
Appellants' invention generally relates to an external memory
controller that routes requests to a remote memory node. See Abstract.
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. A computing system, comprising:
a computing node comprising:
a plurality of processors, including a selected
processor; and
a master memory controller, the master memory
controller external to the plurality of processors; and
a remote memory node coupled to the computing node via
a system fabric, and comprising:
remote memory; and
a remote memory controller,
wherein the master memory controller receives a first
request from the selected processor to access local memory to the
selected processor, routes a corresponding second request to
access the remote memory as the local memory across the system
fabric to the remote memory node, and returns a first response to
the selected processor after receiving a corresponding second
response to the corresponding second request from the remote
memory node across the system fabric.
App. Br. 8 (Claims Appendix).
Appellants appeal the following rejections:
Claims 1, 3, 5-9, and 11-15 are rejected under 35 U.S.C. § 103 as
being unpatentable over Clark et al. (US 2007/0226424 Al, pub. Sept. 27,
2007) and Kumar et al. (US 2011/0131373 Al, pub. June 2, 2011). Final
Act. 3.
Claims 4 and 10 are rejected under 35 U.S.C. § 103 as being
unpatentable over Clark, Kumar, and Garcia et al. (US 6,493,343 Bl, iss.
Dec. 10, 2002). Id. at 9.
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Appeal 2018-007568
Application 14/780,389
Appellants do not appeal the following rejection maintained by the
Examiner (App. Br. 4):
Claims 6-11 are rejected under 35 U.S.C. § 112(b) as being indefinite
for failing to particularly point out and distinctly claim the subject matter
which the inventors regard as the invention. Final Act. 2.
We review the appealed rejections for error based upon the issues
identified by Appellants and in light of the arguments and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential).
ANALYSIS
Rejection under§ 103 of Claims 1 and 3-15
Appellants contend Clark fails to teach or suggest "a master memory
controller, the master memory controller external to the plurality of
processors; ... wherein the master memory controller receives a first request
from the selected processor to access local memory to the selected
processor, [and] routes a corresponding second request to access the remote
memory as the local memory across the system fabric to the remote memory
node," as recited in claim 1. App. Br. 5-6; Reply Br. 1-2. Specifically,
Appellant argues, "in the claim language, it is the master memory controller
that receives a first request from a selected processor of the computing node
and routes a corresponding second request to the remote memory node."
Reply Br. 1. In contrast, Appellant argues, Clark's "directories just store
information-they do not perform any request routing, response routing, and
so on." Id. at 2.
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Appeal 2018-007568
Application 14/780,389
The Examiner relies on Clark's "directory of node O" to teach the
claimed "master memory controller." Final Act. 4. Specifically, the
Examiner finds that "Clark['s] Fig[.] 2B clearly discloses a system of two
nodes: Node O and Node 1 which is remote from the[] Node O; ... each node
having memory controlling logic which is represented as Directory NO and
directory NI." Ans. 14. However, Clark describes these nodal directories as
merely "track[ing] copies of blocks from memory 212 that are cached at
other nodes" so as to "only inform those processors currently playing an
active role in the use of a given address about an operation to that address."
Clark ,r,r 33, 35. In other words, Clark's nodal directory merely stores
information, i.e., about addresses that are cached. We therefore agree with
Appellants that Clark's "directories just store information-they do not
perform any request routing [or] response routing" and thus do not disclose
the master memory controller as claimed. See Reply Br. 2. Accordingly, we
do not sustain the Examiner's rejection of claim 1 and corresponding
dependent claims 3-5.
Claim 6 similarly recites "receiving, in an external memory controller
of a computing node including a processor, a first request from the processor
to access remote memory as local memory to the processor, ... [and]
routing, by the external memory controller, a second request corresponding
to the first request from the processor." For similar reasons stated forth
above with respect to claim 1, we also do not sustain the Examiner's
rejection of claim 6 and corresponding dependent claims 7-11.
Claim 12 similarly recites "a master memory controller included in
the computing node to receive first requests to access local memory ... , the
master memory controller external to the processors; ... wherein the master
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Appeal 2018-007568
Application 14/780,389
memory controller routes to the slave memory controller second requests to
access the remote memory as the local memory, the second requests
corresponding to the first requests." For similar reasons stated forth above
with respect to claim 1, we also do not sustain the Examiner's rejection of
claim 12 and corresponding dependent claims 13-15.
Rejection under§ 112(b) of Claims 6-11
Appellants do not appeal the Examiner's rejection of claims 6-11 as
being indefinite. App. Br. 4 ("Claims 6-10 have also been rejected ... as
being indefinite, but Applicant without prejudice is not appealing this
rejection"); see Ans. 3 (maintaining § 112(b) rejection). Accordingly, we
proforma sustain the Examiner's § 112(b) rejection of claims 6-11. See
Frye, 94 USPQ2d at 1075 (The Board "reviews ... rejection[s] for error
based upon the issues identified by appellant, and in light of the arguments
and evidence produced thereon," and treats arguments not made as waived.).
DECISION
We reverse the Examiner's 35 U.S.C. § 103(a) rejection of claims 1
and 3-15.
We affirm the Examiner's 35 U.S.C. § 112(b) rejection of claims 6-
1 1.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED-IN-PART
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