Ex Parte Gaertner et al

Board of Patent Appeals and Interferences

Feb 10, 2009

10900537 (B.P.A.I. Feb. 10, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte UTE GAERTNER, ERWIN PFEFFER, and CHARLES F. WEBB
____________
Appeal 2008-1685
Application 10/900,537
Technology Center 2100
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Decided:1 February 10, 2009
____________
Before JAMES D. THOMAS, LANCE LEONARD BARRY,
and JAY P. LUCAS, Administrative Patent Judges.
THOMAS, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1 through 16. We have jurisdiction under 35 U.S.C.
§ 6(b).

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 CFR § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Data (electronic delivery).
Appeal 2008-1685
Application 10/900,537

We reverse.
INVENTION
A central processing unit in a computer comprises a number of
functional units and at least an additional module for processing function
calls received from one of the function units. A memory within this module
stores a plurality of control instructions and a plurality of branch
instructions. Each of the control instructions has assigned within it an
instruction address for a next sequential instruction. Correspondingly, each
branch instruction has assigned within it at least two alternative instruction
addresses. The respective control and branch instructions are processed
within respective dedicated logic circuitry within the module. (Spec. 2,
[0008-0010]).
REPRESENTATIVE CLAIM
1. A central processing unit comprising:

a) a number of functional units (A, B, . . . , N);

b) at least one module for processing a function call received from
open of the functional units, the module having;

a decoder to obtain an instruction address from the function call;

a memory for storing a plurality of control instructions and for storing
a plurality of branch instructions, each control instruction having an assigned
instruction address for a next instruction and each branch instruction having
assigned at least two alternative instruction addresses for a next instruction;

a first logic circuit from processing the branch instruction in order to
select one of the at least two alternative instruction addresses of one of the
branch instructions; and
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Application 10/900,537

a second logic circuit for processing the control instructions in order
to return a result in response to the function call.

PRIOR ART
The Examiner relies on the following references as evidence of
unpatentability:
Tran US 5,864,689 Jan. 26, 1999
Hilgendorf US 5,974,543 Oct. 26, 1999
Ganapathy US 6,842,850 B2 Jan. 11, 2005
(Filing date Feb. 25, 2003)
Hamacher, Vranesic, Zaky, “Computer Organization,” Second
Edition, McGraw-Hill, 1984, pp. 57-65.

EXAMINER’S REJECTIONS
In a first stated rejection under 35 U.S.C. § 103, the Examiner relies
upon Tran in view of Hamacher as to claims 1, 2, 4, 6, 8 through 12, 14, and
16. In a second stated rejection relying upon these references in addition to
Ganapathy, the Examiner rejects claims 3 and 13. Lastly, in a third stated
rejection of claims 5, 7, and 15, the Examiner relies upon Tran in view of
Hamacher and further in view of Hilgendorf.2

2 Both the final rejection and the Answer as well as the Brief mistake the
actual rejections of the claims on appeal. For the Examiner’s part, the
Examiner considers claims 1 through 16 to be rejected only over Tran and
Hamacher and the Brief follows suite. The Brief and the Reply Brief do not
recognize the actual stated rejections as we have set forth above.
Furthermore, the first stated rejection is inclusive of the evidence relied upon
for unpatentability as to the second and third stated rejections.
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Application 10/900,537

CLAIM GROUPINGS
Based on Appellants’ arguments in the principal Brief on appeal, we
will decide the appeal on the basis of the subject matter commonly set forth
in independent claims 1 and 11 on appeal with respect to the combined
teachings of Tran and Hamacher. Attempts by Appellants to argue the
second stated rejection at pages 12 and 13 of the principal Brief rely in
actuality for patentability upon the alledged deficiencies with respect to Tran
in view of Hamacher as to the first stated rejection.
ISSUE
Have Appellants shown that the Examiner erred in finding that the
combination of Tran and Hamacher teaches the data structure of each control
instruction having an assigned instruction address for a next instruction
within it and each branch instruction having assigned at least two alternative
instruction addresses for a next instruction within it, along with their
corresponding claimed first and second logic circuits?
FINDINGS OF FACT
1. Based upon Appellants’ comments at pages 11 and 12 of the principal
Brief on appeal, Appellants do not argue that Tran and Hamacher are not
properly combinable under 35 U.S.C. § 103, but in turn only argue that the
claimed invention is not taught or suggested by the combination of this
applied prior art.
2. Figures 1 and 2 of Tran show a microprocessor 12 having a
Microcode Unit 45 which processes a special routine of which DSP
functions are inclusive.
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Application 10/900,537

3. Tran teaches at column 2, lines 19 through 21 that “[t]he routines may
be fetched by the microprocessor upon occurrence of a corresponding
instruction.”
4. At column 2, lines 32 and 33, Tran teaches “DSP functions may
simply be called by the program.”
5. Tran also teaches at column 2, lines 45 through 51 “[a] number of
methods for defining instructions indicative of a DSP function are
contemplated. For example, a subroutine call instruction having a target
address within a predefined range of addresses may be defined as indicative
of a DSP function. Alternatively, a special subroutine call instruction may
be added to the instruction set.”
6. Tran also teaches at column 4, lines 42 through 65:

In one embodiment, microprocessor 12 defines subroutine call
instructions having target addresses within a particular range of
addresses to be indicative of DSP functions. A “subroutine call
instruction” is a branch instruction which stores the address of the
following instruction within a predefined storage location.
Instructions residing at the target address of the subroutine call
instruction are executed until a corresponding subroutine return
instruction is executed. The subroutine return instruction, also a
branch instruction, causes instruction execution to continue at the
address stored by the subroutine call instruction. Exemplary
subroutine call and return instructions are the CALL and RET
instruction of the x86 instruction set. For this embodiment,
instruction decode unite 36 includes decoding circuitry for detecting
the subroutine call instructions having target addresses within the
specified range, and circuitry for routing the target address to
microcode unit 45 upon detecting such instructions. Microcode unit
45 identifies the requested function from the target address. In

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another embodiment, a special call instruction encoding is added to
the instruction set recognized by microprocessor 12. The special
encoding is indicative of a DSP function and the associated target
address identifies the routine in microcode unit 45.

7. At column 6, lines 11 through 13, Tran teaches “[i]nstruction cache 32
may additionally include a branch prediction mechanism for predicting
branch instructions as either taken or not taken.”
8. Hamacher teaches in the first full paragraph at the top of page 58:
Any program that requires the use of the subroutine branches to its
starting location. This is usually termed calling the subroutine. After
the subroutine has been executed, it is necessary to return to the
program that called it. Since the subroutine is intended to be called
from different locations in a calling program provision must be made
for branching back, or returning, to the appropriate location. . . . The
way in which any particular computer makes it possible to call and
return from subroutines is referred to as its subroutine linkage
method.

9. Hamacher teaches in paragraph 2.8.1 at page 58 “[t]he simplest
linkage method is to preserve the contents of the PC in a specific location,
for example, memory location LINK. The return to the calling program can
be achieved by branching indirectly through memory location LINK, as
illustrated in Figure 2.23a.” A similar illustration is with respect to
subroutine call depiction in Figure 2.24a.

ANALYSIS
The lengthy positions of Appellants and the Examiner in the Brief,
Answer, and Reply Brief fail to focus upon the issues before us in this
appeal and merely present arguments about arguments, essentially losing
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Application 10/900,537

sight of the forest for the trees. The subject matter of the independent claims
1 and 11 requires, broadly speaking, that any given instruction has a data
structure or architecture that “has”, as a present tense recitation, within its
data fields, an instruction address for the next instruction.
Findings of fact 2 through 7 clearly illustrate that Tran teaches the
basic concept of instructions “having” an assigned next instruction address
within their own data fields. Moreover, the portions of Hamacher are noted
in findings of fact 8 and 9 clearly illustrates the same teaching.
Significantly, Hamacher shows in figures 2.23a the use of the word
“indirect” which is consistent with the textual teaching at page 58 that a
return to a calling program is achieved by branching “indirectly” through a
memory location that is illustrated in this figure. Both Tran and Hamacher
teach what is well known in the art as indirect addressing.
On the other hand, we have found no teaching in Tran, and none in
Hamacher, that teaches a branch instruction having assigned within it at least
two alternatives instruction addresses for a next instruction. This feature of
both independent claims 1 and 11 on appeal must not be considered alone. It
is the claimed first logic circuit that actually makes the determination or
selection, as claimed, of which of the least two alternative instruction
address set forth in the branch instruction will be implemented.
Therefore, the Examiner has failed to set forth a prima facie case of
obviousness of the subject matter of independent claims 1 and 11 on appeal
as to this recited feature. Since the Examiner has not shown that Ganapathy
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and Hilgendorf in the second and third stated rejections of the claims on
appeal contain this feature, the rejection of them as well as all dependent
claims is also reversed.

CONCLUSION OF LAW
Appellants have shown that the Examiner erred in finding that the
combination of Tran and Hamacher teaches the subject matter of
independent claims 1 and 11 on appeal and, as such, the subject matter of all
the dependent claims.

DECISION
The Examiner’s three stated rejections of independent claims 1
through 16 are reversed.

REVERSED

pgc

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