Ex Parte Foo

Patent Trial and Appeal Board

Jul 18, 2018

14177980 (P.T.A.B. Jul. 18, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/177,980 02/11/2014
104840 7590 07/20/2018
Imagination Technologies
c/o Vorys, Sater, Seymour and Pease LLP
1909 K St., NW
Ninth Floor
Washington, DC 20006
FIRST NAMED INVENTOR
Yoong Chert Foo
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
070852.000224 2179
EXAMINER
PAN, DANIEL H
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
07/20/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patlaw@vorys.com
vmdeluca@vorys.com
rntisdale@vorys.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YOONG CHERT FOO
(Applicant: Imagination Technologies Limited)
Appeal2017-008778
Application 14/177,980 1
Technology Center 2100
Before JOHN A. EV ANS, NORMAN H. BEAMER,
and JOHN D. HAMANN, Administrative Patent Judges.
BEAMER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1-8. We have jurisdiction over the pending
rejected claims under 35 U.S.C. § 6(b ).
We affirm.
1 Appellant identifies Imagination Technologies Limited as the real party in
interest. (App. Br. 1.)
Appeal2017-008778
Application 14/177 ,980
THE INVENTION
Appellant's disclosed and claimed invention is directed to
synchronizing execution of a plurality of threads on a multi-threaded
processor. (Abstract.) Independent claim 1, reproduced below, is
illustrative of the subject matter on appeal:
1. A multi-threaded processor system, comprising:
a plurality of data processing cores configured to
simultaneously execute multiple threads for a program;
an instruction decode unit configured to decode
program instructions to be used to configure the plurality
of data processing cores, and to generate an indication
when a thread that is executing program instructions
which is to be synchronized with other threads of the
multiple threads, branches around a section of program
instructions, while the other threads do not branch around
a section of program instructions; and
a control core coupled with the instruction decode
unit to receive the indication and to control which threads
are to execute on which of the plurality of data
processing cores, the control core comprising non-
transitory memory containing status data for a plurality
of threads, of which the multiple threads are a subset,
wherein a number of threads in the plurality of
threads is greater than a number of the multiple threads
that are a subset of the plurality of threads, and the status
data comprises, for each thread of the subset of the
plurality of threads, an indication whether it is waiting to
be synchronized, and
the control core is responsive to receiving the
indication, by updating the status data for the thread to
which the indication pertains, and to swap a thread from
the plurality of threads to be executed by the plurality of
data processing cores, which is not waiting for
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Application 14/177 ,980
synchronization with any other thread of the plurality of
threads.
REJECTION
The Examiner rejected claims 1-8 under 35 U.S.C. § I03(a) as being
unpatentable over Coon et al. (US 7,543,136 Bl, issued June 2, 2009) and
Kessler et al. (US 5,721,921, issued Feb. 24, 1998). (Final Act. 3-10.)
ISSUES ON APPEAL
Appellant's arguments in the Appeal Brief present the following
issue: 2
Whether the Examiner erred in finding the combination of Coon and
Kessler teaches or suggests the limitations of claims 1-8. (App. Br. 5-10.)
ANALYSIS
We have reviewed the Examiner's rejections in light of Appellant's
arguments that the Examiner erred. We disagree with Appellant's
arguments, and we adopt as our own ( 1) the pertinent findings and reasons
set forth by the Examiner in the Action from which this appeal is taken
(Final Act. 3-10) and (2) the corresponding findings and reasons set forth by
the Examiner in the Examiner's Answer in response to Appellant's Appeal
2 Rather than reiterate the arguments of Appellant and the positions of the
Examiner, we refer to the Appeal Brief (filed Jan. 24, 2017) (herein, "App.
Br."); the Reply Brief (filed May 30, 2017) (herein, "Reply Br."); the Final
Office Action (mailed July 22, 2016) (herein, "Final Act."); and the
Examiner's Answer (mailed Mar. 28, 2017) (herein, "Ans.") for the
respective details.
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Application 14/177 ,980
Brief. (Ans. 9--12.) We concur with the applicable conclusions reached by
the Examiner, and emphasize the following.
In finding that Coon and Kessler teach or suggest the limitations of
the claims, the Examiner relies on the disclosure in Coon of a system for
managing divergent threads using synchronization tokens with masks that
indicate which threads in a group of threads are actively executing
instructions in one instruction branch (the "taken" branch), and which
threads are disabled because of divergence (from the "not-taken" branch).
(Final Act. 3--4; Coon Abstract, Figs. 3A, 6B, col. 5, 1. 21---col. 9, 1. 6, and
col. 15, 1. 3---col. 17, 1. 4.) The Examiner also relies on the disclosure in
Kessler of a method of "barrier synchronization" in a massively parallel
processing system, which can be implemented as a plurality of threads, with
provisions for swapping in new job instantiations when a job reaches a
barrier point, in order to provide more efficient utilization of computational
resources. (Final Act. 5; Kessler Abstract, col. 5, 1. 62---col. 6, 1. 5, and col.
6, 11. 31--47.)
Appellant argues the Examiner errs because Coon and Kessler address
different scenarios and have fundamental differences in approach. (App. Br.
8.) For example, Coon uses masks that indicate the status of threads within
thread groups, independent of threads in other thread groups, and in contrast
Kessler discloses swapping job instantiations. (App. Br. 8-9.) Thus,
Appellant argues, "use of a barrier for synchronization of jobs in Kessler is
not analogous to use of a synchronization token in response to a 'set-
synchronization' bit in a fetched branch instruction in Coon for
synchronizing of threads in a thread group." (App. Br. 9.)
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Application 14/177 ,980
However, we are not persuaded the Examiner errs in applying the
swapping teachings of Kessler to the multithreading system of Coon:
It would have been obvious to one of ordinary skill in the
art to use Kessler in Coon for swapping a thread from the
plurality of threads to be executed by the plurality of data
processing cores, which is not waiting for synchronization with
any other thread of the plurality of threads, as claimed, for the
purpose of providing more efficient utilization of computational
resources ....
(Final Act. 5.) Appellant does not point to any evidence of record that the
resulting combination would be "uniquely challenging or difficult for one of
ordinary skill in the art" or "represented an unobvious step over the prior
art." Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed.
Cir. 2007) (citing KSR Int 'l Co. v. Teleflex Inc., 550 U.S. 398, 418-19
(2007)). The Examiner's findings are reasonable because the skilled artisan
would "be able to fit the teachings of multiple patents together like pieces of
a puzzle" because the skilled artisan is "a person of ordinary creativity, not
an automaton." KSR, 550 U.S. at 420-21. We are persuaded the claimed
subject matter exemplifies the principle that "[t ]he combination of familiar
elements according to known methods is likely to be obvious when it does
no more than yield predictable results." KSR, 550 U.S. at 416.
Appellant further argues that the combination of Coon and Kessler
does not result in the claimed subject matter, because applying the swapping
teachings of Kessler to Coon would result in an entire thread group being
swapped out, as the swapping of Kessler involves an entire job instantiation.
However, "the test for obviousness is not whether the features of a
secondary reference may be bodily incorporated into the structure of the
primary reference." In re Keller, 642 F.2d 413,425 (CCPA 1981). Instead,
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Application 14/177 ,980
the relevant issue is "what the combined teachings of the references would
have suggested to those of ordinary skill in the art." Id. "Combining the
teachings of references does not involve an ability to combine their specific
structures." In re Nievelt, 482 F.2d 965, 968 (CCPA 1973). We are not
persuaded the Examiner errs in finding:
Conn already teaches his active mask is set which activates five
threads that need to execute the else-side of the branch and
disabling the three threads that execute the if-side of the branch
( see col.15, lines 15-26). The "if' and "else" itself shows the
swapping of the individual threads, such as activating/disabling
more/less threads in the else-side/if-side of the branch.
Therefore, in Coon, no entire thread group would be needed to
be swapped out. Nevertheless, appellant is kindly reminded
that unclaimed features cannot be used to overcome the prior art
.... For example, nowhere does applicant claim recite whether
an entire group of threads is or not to be swapped out.
(Ans. 11.)
Appellant further argues "there is no ... indication of branching
around a portion of instructions in either Coon or Kessler." (App. Br. 10.)
Not so -the use of the various "Sync," "Divergence," and "Call" tokens in
Coon provide such indication. (Coon Fig. 6B, col. 11, Table 4, col. 16, 11.
19--25.) Appellant also argues there would be no reason to swap threads
from outside a thread group in Coon, because to do so would tie one thread
group to another, whereas Coon teaches that the thread groups are
independent. (App. Br. 10.) However, the multithreaded processing units of
Coon may be configured to process more than one thread group, and so
swapping in a thread from one group in place of a disabled thread in another
group is at least taught or suggested in light of the teachings of Kessler.
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Accordingly, we sustain the Examiner's obvious rejection of claims
1-8 over the combination of Coon and Kessler.
DECISION
We affirm the Examiner's decision rejecting claims 1-8.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv). See
37 C.F.R. § 4I.50(f).
AFFIRMED
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