Ex Parte Fineberg et alDownload PDFPatent Trial and Appeal BoardOct 29, 201311243848 (P.T.A.B. Oct. 29, 2013) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte SAMUEL A. FINEBERG, PANKAJ MEHRA, RAHUL NIM, and TOM A. HEYNEMANN ____________ Appeal 2011-004400 Application 11/243,848 Technology Center 2400 ____________ Before JOSEPH L. DIXON, ST. JOHN COURTENAY III, and CARLA M. KRIVAK, Administrative Patent Judges. COURTENAY, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-004400 Application 11/243,848 2 STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of claims 1-4, 7-10, 13, 14, 16-20, 24, 27-29, 31, 38, and 45-47. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. INVENTION This invention on appeal relates to remote configuration of persistent memory system access and translation tables (ATT). (Spec. ¶[0005]). Claim 1, reproduced below, is illustrative of the claimed subject matter: 1. A method for remotely configuring a network persistent memory unit (nPMU), comprising: [a] issuing a first command to the nPMU from a persistent memory manager (PMM) device, the PMM remotely located from the nPMU, and the first command indicates that the PMM has authority to control the nPMU; and [b] enabling remote direct memory access (RDMA) of a processor node to the nPMU, the processor node remotely located from the nPMU, [c] the enabling by: populating memory of the nPMU by the PMM, [c1] the populating without involvement from an nPMU processor. (Disputed limitation emphasized, steps lettered). Appeal 2011-004400 Application 11/243,848 3 REJECTIONS R1. The Examiner rejected claims 1-4, 7, 10, 45, and 46 under 35 U.S.C. § 103(a) based upon the teachings of Mehra (U.S. Patent Application Publication No. 2004/0148360 A1) and Gregg (U.S. Patent No. 6,442,613 B1). R2. The Examiner rejected claims 8, 13, 14, 24, 28, and 29 under 35 U.S.C. § 103(a) based upon the combined teachings and suggestions of Mehra, Gregg, and Hitomi (U.S. Patent No. 7,024,463 B1). R3. The Examiner rejected claim 9 under 35 U.S.C. § 103(a) based upon the combined teachings and suggestions of Mehra, Gregg, and Owen (U.S. Patent Application Publication No. 2002/0103945 A1). R4. The Examiner rejected claims 16-20 under 35 U.S.C. § 103(a) based upon the combined teachings and suggestions of Mehra, Gregg, Hitomi, and Hansen (U.S. Patent Application Publication No. 2005/0132250 A1). R5. The Examiner rejected claims 27 and 31 under 35 U.S.C. § 103(a) based upon the combined teachings and suggestions of Mehra, Gregg, Hitomi, and Fineberg (U.S. Patent Application Publication No. 2005/0216552 A1). R6. The Examiner rejected claim 38 under 35 U.S.C. § 103(a) based upon the combined teachings and suggestions of Mehra and Hitomi. R7. The Examiner rejected claim 47 under 35 U.S.C. § 103(a) based upon the combined teachings and suggestions of Mehra, Gregg, and Fineberg. Appeal 2011-004400 Application 11/243,848 4 ANALYSIS R1. CLAIM 1 UNDER § 103 Regarding disputed claim 1 limitations (emphasis added): [b] enabling remote direct memory access (RDMA) of a processor node to the nPMU, the processor node remotely located from the nPMU, [c] the enabling by: populating memory of the nPMU by the PMM, [c1] the populating without involvement from an nPMU processor, Appellants contend Gregg would not have taught or suggested limitations [b], [c], and [c1] because Gregg does not require the processors in the channel adaptors/Direct Memory Adapter (DMA) engine “are not involved in enabling the DMA (as opposed to performing the DMA).” (Reply Br. 2). Gregg describes: Channel adapters 118, 120, 122 are, for instance, direct memory adapter (DMA) engines, which move data to and from memory 108, 112 without any direct involvement of any of processors 106, 110. They also provide protection from the peripherals or other components storing in any arbitrary location in memory. The peripherals or other components can only store into the memory locations known to the channel adapters, and those locations are determined by the programs running in processors 106, 110. The channel adapters are considered a trusted, integral part of the central processing complex. (Gregg, col. 5, ll. 24-35) (emphases added). Appellants' contentions are persuasive. First, Gregg's DMA engines 118 move data to and from memories 108, 112. (Gregg, col. 5, ll. 24-35). However, Gregg's description of moving data to and from memory does not correspond to limitation's [c] and [c1] because limitation [c] "populating memory of the nPMU by the PMM" is a specific configuration step (claim 1 Appeal 2011-004400 Application 11/243,848 5 preamble) in [b] "enabling remote direct memory access (RDMA) . . . the enabling by populating memory of the nPMU by the PMM." (Claim 1; Spec. ¶[0052], ¶[0060]). Second, Appellants contend it is logical that Gregg's "processors 106 and 110 communicate with the processors of the [DMA engine] channel adapters to inform them of the specific areas each I/O device 116 can access using DMA, and the processors of the [DMA engine] channel adapters implement the limited access DMA to the memory 108, 112." (App. Br. 14; Gregg, col. 5, ll. 24-28). We are persuaded by Appellants' contention. The plain meaning of negative limitation [c1] "the populating without involvement from an nPMU processor" precludes populating using a DMA engine processor ("an nPMU processor"). Specifically, Gregg's DMA engine processor corresponds to an "nPMU processor" because the DMA engine is in the nPMU (network persistent memory unit). (See Ans. 4-5; Gregg col. 5, ll. 24-28; Gregg Fig 1; Appellants' Fig. 8; DMA engine 114, nPMU 110e; claim 1). Gregg fails to teach or suggest limitation [c1] because Gregg is silent regarding the role of the DMA engine processor ("an nPMU processor") during populating/configuration of the memory of the nPMU. For these reasons, on this record, we are persuaded of Examiner error. Accordingly, we reverse the rejection R1 of claim 1, and the rejections R2, R3, and R7 of the claims that depend from claim 1. R2. CLAIM 13 UNDER § 103 Regarding the rejection R2 of independent claim 13, including the limitation: Appeal 2011-004400 Application 11/243,848 6 the network interface is configured to receive information over the network from a persistent memory manager (PMM) device, and to populate the memory location translation information based on the information received, the receipt from the PMM and population of the memory location translation information without involvement of the processor, Appellants contend claim 13 is patentable for similar reasons asserted for the commensurate limitations in claim 1. (App. Br. 15-17). We are persuaded of Examiner error regarding claim 13 for the same reasons discussed above regarding claim 1. We therefore reverse the rejection R2 of independent claim 13, and claims 14, 24, 28, and 29 that depend from claim 13. Regarding rejections R4 (claims 16-20) and R5 (claims 27 and 31), the Examiner has not established that the additional cited references overcome the aforementioned deficiencies of Gregg, as discussed above regarding rejection R1. Therefore, we also reverse rejections R4 and R5. R6. CLAIM 38 UNDER § 103 Regarding claim 38 limitations: [a] populate a first memory of the nPMU device with parameters, [b] the population by remote direct memory access (RDMA) to the first memory, and [c] the parameters enable RDMA operations to a second memory of the nPMU, and [d] the parameters enable translation of network address to physical addresses of within the first memory, (emphasis added), Appellants contend, "Mehra appears to be silent as to whether the Mehra system uses RDMA to perform programming to make RDMA communications possible" and Mehra could use non- RDMA exchange to populate the nPMU memory. (Reply Br. 3). Appeal 2011-004400 Application 11/243,848 7 We are persuaded by Appellants' contention. We agree the Examiner's cited sections of Mehra (Ans. 23 citing to ¶[0020], ¶[0028]) would not have taught or suggested the PMM uses "remote direct memory access (RMDA)" to populate the first memory because "RDMA" is enabled after the memory/logic in the Network Interface (NI) 108 of the nPMU 110 is programmed by the PMM over the RDMA enabled SAN to enable virtual- to-physical memory support. (Mehra, ¶[0029], ll. 1-5; ¶[0020], ll. 9-10). For these reasons, on this record, we are persuaded of Examiner error. Accordingly, we reverse the rejection R6 of claim 38. DECISION We reverse the Examiner's rejections R1- R7 of claims 1-4, 7-10, 13, 14, 16-20, 24, 27-29, 31, 38, and 45-47 under § 103. REVERSED llw Copy with citationCopy as parenthetical citation