Ex Parte Drescher et al

Board of Patent Appeals and Interferences

Apr 13, 2009

10139733 (B.P.A.I. Apr. 13, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte WOLFRAM DRESCHER AND UWE PORST
____________________

Appeal 2008-2555
Application 10/139,733
Technology Center 2100
____________________

Decided:1 April 13, 2009
____________________

Before ALLEN R. MACDONALD, JEAN R. HOMERE, and JAMES R.
HUGHES, Administrative Patent Judges.

HUGHES, Administrative Patent Judge.

DECISION ON APPEAL

1 The two month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
Appeal 2008-2555
Application 10/139,733
STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-8 and 10.2 We have jurisdiction under 35 U.S.C. § 6(b)
(2002).
We REVERSE.

Appellants’ Invention
Appellants aver that they invented an address-generating arrangement
(system) for a microprocessor including two address-generating units (a base
address-generating unit and an address-generating expansion unit) and an
interface. (Spec. [0001], [0006]-[0008].) The base address-generating unit
includes two or more base registers and one or more base arithmetic units.
The base address-generating unit outputs an address with a width (bit length)
equal to the complete width of an address register useable in program
execution. The address-generating expansion unit also outputs an address
with a width equal to the complete width of an address register useable in
program execution. The interface selectively connects one of the outputs
(base address-generating unit output or address-generating expansion unit
output) to one of the base registers (in the base address-generating unit), so
that the base address-generating unit and the address-generating expansion

2 Appellants also argue for the entry of claim 11 – an independent claim
added after final rejection by the Examiner of claims 1-8 and 10. (App. Br.
9, 14-15.) The non-entry of a claim is petitionable subject matter, as
explained by the Examiner. (Ans. 8.) Accordingly, claim 11, and its
non-entry will not be addressed in this appeal.
2
Appeal 2008-2555
Application 10/139,733
unit independently generate an address useable in microprocessor program
execution. (Spec. [0012]-[0015]; App. Br. 6.)3
Claims
Independent claim 1 is illustrative of the invention, and reads as
follows:
1. An address-generating arrangement for a
microprocessor comprising:
a base address-generating unit including a plurality of
base registers and at least one base arithmetic unit having an
address output, said address output including a first address,
wherein said first address is a complete address having width
equal to the width of an address register useable in program
execution;
an address-generating expansion unit having an address
bus output, said address bus output including a second address
that includes an address extension, wherein said second address
is another complete address having width equal to the width of
the address register useable in program execution; and
an interface for selectively connecting one of said
address output and said address bus output to one of said
plurality of base registers in said base address-generating unit,
wherein said base address-generating unit and said address-
generating expansion unit are configured to substantially
independently generate complete addresses namely said first
and second addressees useable in microprocessor program
execution, respectively.

3 Reference is made to Appellants’: Specification (“Spec.”); Amended
Appeal Brief (“App. Br.”) dated July 6, 2007; and Reply Brief (“Reply Br.”)
dated November 5, 2007. Reference is also made to the Examiner’s Answer
(“Ans.”) mailed September 4, 2007.
3
Appeal 2008-2555
Application 10/139,733
References
The Examiner relies on the following reference as evidence of
unpatentability:
Taniai US 5,203,006 Apr. 13, 1993

Rejections
The Examiner rejected claims 1-8 and 10 under 35 U.S.C. § 102(b) as
being unpatentable over Taniai.

Appellants’ Contentions
Appellants contend that the Examiner improperly rejected the claims,
and the cited reference does not disclose a base address-generating unit
including two or more registers and an arithmetic unit, or an address-
generating expansion unit including a register and an arithmetic unit. (App.
Br. 13.)

Examiner’s Findings and Conclusions
The Examiner found that Taniai discloses each feature of Appellants’
claim 1, including a first and second address generator, and an interface.
(Ans. 4-5.) The Examiner found that the address generators include at least
two registers – the first to hold an address (to be incremented) and the
second to hold an incrementing value – and an arithmetic unit to add the
register values together to generate the next address. (Ans. 5 and 8.)

4
Appeal 2008-2555
Application 10/139,733
ISSUE
Did Appellants establish the Examiner erred in determining that
Taniai discloses each feature of Appellants’ invention, in particular, an
address-generating unit including two or more registers and an arithmetic
unit?

FINDINGS OF FACT (FF)
The following findings of fact relevant to the rejections under review
are made based on a preponderance of evidence on the record:

Appellants’ Invention
1. Appellants invented an address-generating arrangement for a
microprocessor including a base address-generating unit, an address-
generating expansion unit, and an interface. (Spec. [0001], [0006]-[0008].)
2. One embodiment of Appellants’ invention includes a base
address-generating unit with two or more base registers and a base
arithmetic unit. (Spec. [0012].)
3. One embodiment of Appellants’ invention includes an address-
generating expansion unit with at least one expansion register and an
expansion arithmetic unit. (Spec. [0013].)
4. The base address-generating unit outputs an address with a
width (bit length) equal to the complete width of an address register useable
in program execution. (Spec. [0013]-[0015]; App. Br. 6-7.)
5
Appeal 2008-2555
Application 10/139,733
5. The address-generating expansion unit outputs an address with
a width equal to the complete width of an address register useable in
program execution. (Spec. [0013]-[0015]; App. Br. 6-7.)
6. The interface selectively connects one of the outputs (base
address-generating unit output or address-generating expansion unit output)
to one of the base registers (in the base address-generating unit), so that the
base address-generating unit and the address-generating expansion unit
independently generate an address useable in microprocessor program
execution. (Spec. [0007], [0012]-[0015]; App. Br. 7-8.)

Taniai Reference
7. Taniai discloses an address-generating arrangement for a
microprocessor including a first address generator (Fig. 4, element 22), a
second address generator (Fig. 4, element 24), and an interface (selector –
Fig. 4, element 26). (Col. 3, l. 64 to col. 5, l. 31.)
8. Taniai discloses that the first address generator outputs an
address (continue address) with a width (bit length) equal to the complete
width of an address register useable in program execution. (Col. 3, l. 64 to
col. 5, l. 19.)
9. Taniai discloses that the second address generator outputs an
address (branch address) with a width (bit length) equal to the complete
width of an address register useable in program execution. (Col. 4, ll. 4-31.)
10. Taniai discloses that the interface selectively connects the
output of the first address generator or the second address generator to the
6
Appeal 2008-2555
Application 10/139,733
output (Fig. 4, element 27). (Col. 4, ll. 12-31.) The output is a register – it
obtains, holds, and outputs the address from the selector. (Col. 4, ll. 12-31.)
The first address generator and the second address generator independently
generate an address useable in microprocessor program execution. (Col. 3, l.
64 to col. 5, l. 31.)

PRINCIPLES OF LAW
Anticipation
Anticipation is a question of fact. In re Schreiber, 128 F.3d 1473,
1477 (Fed. Cir. 1997). Under 35 U.S.C. § 102, “[a] claim is anticipated only
if each and every element as set forth in the claim is found, either expressly
or inherently described, in a single prior art reference.” Verdegaal Bros.,
Inc. v. Union Oil Co. of Cal., 814 F.2d 628, 631 (Fed. Cir. 1987); see
Perricone v. Medicis Pharm. Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005)
(citation omitted).
Anticipation by inherent disclosure is “appropriate only when the
reference discloses prior art that must necessarily include the unstated
limitation;” otherwise, the reference “cannot inherently anticipate the
claims.” Transclean Corp. v. Bridgewood Servs., Inc., 290 F.3d 1364, 1373
(Fed. Cir. 2002) (emphasis in original); see In re Robertson, 169 F.3d 743,
745 (Fed. Cir. 1999).

7
Appeal 2008-2555
Application 10/139,733
ANALYSIS
Appellants confine their arguments to claims 1 and 2 (App. Br. 12),
and we so confine our analysis. The Examiner rejects the claims over
Taniai, asserting that Taniai anticipates every limitation of Appellants’
claims. Appellants assert that Taniai does not inherently disclose certain
features of their claims. For the reasons that follow, we agree with
Appellants, and we reverse the Examiner’s rejection of claims 1-8 and 10.
It is undisputed that claim 1 recites, and Taniai discloses, an address-
generating arrangement for a microprocessor including a base address-
generating unit (first address generator), an address-generating expansion
unit (second address generator), and an interface (selector). (FF 1-7; Ans. 4-
5.) The address-generating units (address generators) independently
generate and output a complete address (an address useable in
microprocessor program execution). (FF 4-6, FF 8-10; Ans. 4-5.)
The Examiner and the Appellants agree that claim 1 recites the base
address-generating unit including two or more (a plurality of) base registers
and a base arithmetic unit (FF 2), and the interface selectively connecting the
output of the base address-generating unit and the output of the address-
generating expansion unit to one of the plurality of base registers in the base
address-generating unit (FF 6). The Examiner and the Appellants also agree
that claim 2 recites the additional limitation that the address-generating
expansion unit includes at least one expansion register and an expansion
arithmetic unit. (FF 3.) We find that Taniai discloses an interface
8
Appeal 2008-2555
Application 10/139,733
selectively connecting outputs of the address generators to a register
(output). (FF 10.)
The Appellants assert and the Examiner concedes that Taniai does not
explicitly disclose the registers or arithmetic unit (ALU) of the base address-
generating unit (or the address-generating expansion unit). The Examiner,
however, found that these features were inherent in Taniai’s disclosure, and
that the interface selectively connects to one of the plurality of registers in
the base address-generating unit. (Ans. 4-5 and 8.) Specifically, the
Examiner found that Taniai (inherently) discloses:
[a] plurality of base registers and at least one base arithmetic unit are
inherently present in both the base address-generating unit and the
address-generating expansion unit. Both the base address-generating
unit and the address-generating expansion unit have to include, at
least two registers in order to hold the last address and to hold the
incrementing value; and at least one arithmetic unit (ALU) to add
them together to generate the next address, in each.
(Ans. 5.) In spite of the Examiner’s finding that Taniai does not discuss any
gate level circuitry, the Examiner still found that “any address increment
circuit” requires that “there has to be at least the same number of flip-flops
as the number of address bits in order to hold the current (incremented)
address value,” and concluded that the “flip-flop (the one-bit memory) is
equated with the claimed register(s) since both hold the value for one (or
more) clock cycle(s).” (Ans. 8.) The Examiner also found that Taniai
inherently discloses the registers and arithmetic unit (ALU) of the address-
generating expansion unit. (Ans. 5 and 8.) Specifically, the Examiner found
that the branch address generating circuit refers to a branch address table in
9
Appeal 2008-2555
Application 10/139,733
response to signals Fa through Fn and FD, and generates a corresponding
branch address JA, and concluded that an “arithmetic logic or logic unit
needs to be involved in order to generate the JA using FD and Fa through
Fn.” (Ans. 8.) We disagree with the Examiner, and find the register and
ALU features are not inherently disclosed in Taniai.
Anticipation by inherent disclosure requires that any information
missing from the reference must necessarily be present in the subject matter
of the reference, and it must be so recognized by persons of ordinary skill in
the art. “[A]nticipation by inherent disclosure is appropriate only when the
reference discloses prior art that must necessarily include the unstated
limitation;” otherwise, the reference “cannot inherently anticipate the
claims.” Transclean Corp. v. Bridgewood Servs., Inc., 290 F.3d at 1373
(emphasis in original); see Hitzeman v. Rutter, 243 F.3d 1345, 1355 (Fed.
Cir. 2001); In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999). When a
claim limitation is not explicitly disclosed in a purportedly anticipatory
reference, evidence (extrinsic to the reference) “‘must make clear that the
missing descriptive matter is necessarily present in the thing described in the
reference, and that it would be so recognized by persons of ordinary skill.’”
Robertson, 169 F.3d at 745 (quoting Continental Can Co. USA, Inc., v.
Monsanto Co., 948 F.2d 1264, 1268 (Fed. Cir. 1991)). “It is not sufficient if
a material element or limitation is ‘merely probably or possibly present’ in
the prior art. In re Omeprazole Patent Litigation, 483 F.3d 1364, 1378 (Fed.
Cir. 2007) (J. Newman dissenting) (quoting Trintec Indus., Inc. v. Top-
U.S.A. Corp., 295 F.3d 1292, 1295 (Fed. Cir. 2002); see also Robertson, 169
10
Appeal 2008-2555
Application 10/139,733
F.3d at 745 (quoting Continental Can Co. USA, Inc., 948 F.2d at 1269 and
In re Oelrich, 666 F.2d 578, 581 (CCPA 1981)) (Inherency cannot not be
established “by probabilities or possibilities.”).
Applying these principles, it is incorrect to hold that Taniai
“inherently anticipates” Appellants’ claims. As explained by the Examiner
(Ans. 8), it is well known in the electronics arts to create a counter or a shift
register (incrementing circuit) using cascaded flip-flops and a clock input.
That Appellants’ claimed plurality of registers and arithmetic unit (ALU)
“could be” or “may be” present in Taniai’s disclosed increment circuit and
branch address generating circuit is not sufficient to establish inherency,
notwithstanding that incrementing circuits are well known in the art. In
finding anticipation by inherency, the Examiner ignored these critical
principles. The Examiner made no attempt to show (using evidence
extrinsic to Taniai), that the increment circuit and branch address generating
circuit of Taniai included a plurality of registers and an arithmetic unit
(ALU), or that an artisan of ordinary skill would so recognize. Accordingly,
we find that the Examiner incorrectly determined that Taniai inherently
anticipates Appellants’ claims.

CONCLUSION OF LAW
Appellants established that the Examiner erred in determining Taniai
discloses each feature of Appellants’ invention, in particular, an address-
generating unit including two or more registers and an arithmetic unit.

11
Appeal 2008-2555
Application 10/139,733
DECISION
We reverse the Examiner's rejection of claims 1-8 and 10.

REVERSED

rwk

Baker Botts L.L.P.
30 Rockefeller Plaza, 44th Floor
New York, NY 10112-4498
12