11381870 (P.T.A.B. Sep. 30, 2014)

Ex Parte Dockser

Patent Trial and Appeal BoardSep 30, 2014

11381870 (P.T.A.B. Sep. 30, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte KENNETH ALAN DOCKSER1 ____________ Appeal 2011-007940 Application 11/381,870 Technology Center 2100 ____________ Before FRANCISCO C. PRATS, BRIAN J. MCNAMARA, and JAMES B. ARPIN, Administrative Patent Judges. ARPIN, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1–36. App. Br. 3.2 We have jurisdiction under 35 U.S.C. § 6(b). We reverse. 1 QUALCOMM Incorporated is the real party-in-interest. 2 Throughout this opinion, we refer to (1) the Appeal Brief (App. Br.) filed December 20, 2010; (2) the Examiner’s Answer (Ans.) mailed February 7, 2011; and (3) the Reply Brief (Reply Br.) filed April 7, 2011. Appeal 2011-007940 Application 11/381,870 2 INVENTION Appellant’s invention relates to apparatus and methods for performing sub-precision iterative arithmetic operations. See generally Spec. ¶ 1. In particular, a controlled precision Iterative Arithmetic Logic Unit (IALU), which may be included in a processor, produces sub-precision results, i.e. results having a programmed bit precision (PBP), less than full precision. Id. ¶ 5. In an embodiment, the controlled-precision IALU comprises an arithmetic logic circuit and a precision control circuit. Id. The arithmetic logic circuit iteratively processes operands of a first bit precision to obtain a result. Id. The precision control circuit ends the iterative operand processing when the result achieves sub-precision results, e.g., a programmed second bit precision, less than full bit precision, e.g., the first bit precision. Id.; see id. ¶ 6. The controlled-precision IALU further may comprise rounding logic configured to increment conditionally the result at the least significant bit (LSB) of a sub-precision result, based on the rounding mode, the LSB, and the rounding bits. Id. ¶ 5. In an embodiment, the rounding logic rounds the result by aligning a rounding value with the LSB of the result and conditionally adding the aligned rounding value to the result. Id. The IALU also may truncate one or more of an operand’s LSBs, so that the truncated operands have a bit precision less than the operand’s full precision and greater than or equal to the precision associated with the PBP. See id. ¶ 25. The IALU truncates one or more operand’s LSBs in response to a truncate value received from the precision control unit. Id.; see also id. at Fig. 1 (“TRUNC”). For example, the IALU truncates one or more operand’s LSBs by masking the operand’s LSB(s). See id. ¶ 25. Appeal 2011-007940 Application 11/381,870 3 Four independent claims are pending in this appeal. Claim 1 is directed to a method of performing an iterative arithmetic operation in a processor. App. Br. 13 (Appendix A). Claim 13 is directed to an iterative arithmetic logic unit for use in a processor. Id. at 14. Claim 23 is directed to a processor comprising an iterative arithmetic logic unit. Id. at 15. Claim 36 is directed to an iterative arithmetic logic unit for use in a processor. Id. at 17. Claims 2–12, 34, and 35 depend from claim 1; claims 14–22 depend from claim 13; and claims 24–33 depend from claim 23. Id. at 14–17. Claim 1 is representative and is reproduced below with a disputed element emphasized: 1. A method of performing an iterative arithmetic operation in a processor, comprising: iteratively processing operands of a first bit precision to obtain a result; and ending the iterative processing when the result achieves a programmed second bit precision less than the first bit precision. The Examiner relies on the following references, alone or in combination, as evidence of unpatentability: Reference Name Patent Number Issue Date Arulpragasam US 3,434,114 March 18, 1969 Hirose US 4,839,846 June 13, 1989 Dockser US 5,481,686 June 2, 1996 Pontius US 6,029,243 February 22, 2000 Appeal 2011-007940 Application 11/381,870 4 THE REJECTIONS 1. The Examiner rejects claims 1, 5, 7, 11–13, 16, 18, 22, 23, 26, 32–34, and 36 under 35 U.S.C. § 102(b) as anticipated by Dockser. Ans. 4–9. 2. The Examiner rejects claims 2, 3, 8–10, 14, 15, 19–21, 24, and 27–29 under 35 U.S.C. § 103(a) as unpatentable over Dockser and Hirose. Id. at 9–23. 3. The Examiner rejects claims 4 and 25 under 35 U.S.C. § 103(a) as unpatentable over Dockser and Pontius. Id. at 23–24. 4. The Examiner rejects claims 6, 17, 30, 31, and 35 under 35 U.S.C. § 103(a) as unpatentable over Dockser and Arulpragasam. Id. at 24– 28. ANTICIPATION AND OBVIOUSNESS REJECTIONS BASED ON DOCKSER “A claim is anticipated only if each and every element as set forth in the claim is found, either expressly or inherently described, in a single prior art reference.” Verdegaal Bros., Inc. v. Union Oil Co. of Cal., 814 F.2d 628, 631 (Fed. Cir. 1987). The Examiner finds that Dockser discloses each and every element of claim 1. Ans. 4 (quoting Claim 1). Specifically, the Examiner contends that Dockser discloses the first method step recited in claim 1, namely, “iteratively processing operands of a first bit precision to obtain a result” (emphasis added). Id. (citing Dockser, col. 4, ll. 2–12, 23– 38); see Final Rej. 3. Further, the Examiner contends that Dockser discloses the second method step of claim 1, namely, “ending the iterative processing when the result achieves a programmed second bit precision less than the first bit precision” (emphasis added). Id. (citing Dockser, col. 3, l. 62–col. 4, Appeal 2011-007940 Application 11/381,870 5 l. 12); see Final Rej. 3. The Examiner acknowledges that Dockser describes truncating the full precision of operands to a desired precision prior to beginning processing the operands. Ans. 30. Nevertheless, because rejected claim 5 depends from claim 1 and recites that the method of claim 1 “further comprising truncating one or more least significant bits (LSBs) of the operands before beginning the iterative processing so that the truncated operands have a bit precision less than the first bit precision and greater than or equal to the programmed second bit precision” (emphasis added), the Examiner maintains that independent claim 1 does not exclude and may encompass this additional element. Id. at 33, 35. Thus, the Examiner concludes that Dockser discloses each and every element of claim 1, as well as of the other independent claims. See id. at 3, 6, 7, 9. Appellant argues that the Examiner misunderstands claim 1. App. Br. 6; Reply Br. 2. Claim 1 recites “iteratively processing operands of a first bit precision.” App. Br. 13. Independent claim 13, 23, and 36 include corresponding elements. Id. at 14, 15, 17. According to Appellant, this language requires repeatedly processing operands of a first bit precision and ending the processing when the result of the processing is a “programmed” second bit precision less than the first bit precision. See id. at 6–7; Reply Br. 2–3. Dockser, however, Appellant argues, truncates the operands of a first bit precision to the second bit precision before beginning the processing. App. Br. 7; Reply Br. 3. Appellant relies solely on the arguments with respect to claim 1 to distinguish the rejected claims over Dockser, alone or in combination with other references. App. Br. 10–11. Appeal 2011-007940 Application 11/381,870 6 ISSUE Under § 102(b), does a preponderance of evidence support the Examiner’s finding that Dockser discloses iteratively processing operands of a first bit precision to obtain a result, and ending the iterative processing when the result achieves a programmed second bit precision less than the first bit precision? ANALYSIS 1. Claims 1, 5, 7, 11–13, 16, 18, 22, 23, 26, 32–34, and 36 As noted above, Appellant argues that the language of claim 1 recites that operands of a first bit precision are processed “repeatedly” and that the processing ends when the result of the processing is a “programmed” second bit precision less than the first bit precision. See App. Br. 6–7. Further, Appellant argues that, even if the Examiner is correct that claim 1 must be understood in view of the recitation of claim 5, claim 5 recites that truncating of the operands occurs “before beginning the iterative processing.” App. Br. 7–8; Reply Br. 2–3. Thus, Appellant maintains that claim 5 does not explain how we are to construe the “processing” step, but rather what occurs before the “processing” step. Id. Appellant maintains that Dockser fails to disclose iteratively processing operands of a first bit precision, as recited in claim 1. The Examiner contends that “the claimed limitation ‘iteratively processing operands of a first bit precision’ requires only that operands are in a first bit precision at the start of processing, and that the operands are subsequently processed wherein the processing comprises interative calculations for achieving the result.” Ans. 30 (emphasis added). Referring to the “truncating” language of claim 5, the Examiner concludes that claim 1 Appeal 2011-007940 Application 11/381,870 7 must encompass such truncating, but suggests that, because the precision of the truncated operands, as recited in claim 5, may be greater than3 or equal to the second bit precision, Dockser discloses each and every element of claim 1. Ans. 35. In order to analyze the Examiner’s rejections, we begin by construing the disputed element of claim 1. In construing this element, we apply the broadest reasonable meaning of the words in their ordinary usage, as those words would be understood by one of ordinary skill in the art, taking into account any definitions supplied by Appellant’s Specification. In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). Claim 1 recites that “[a] method of performing an iterative arithmetic operation” includes the step of “iteratively processing operands of a first bit precision to obtain a result.” App. Br. 13. Appellant does not identify a definition of the phrase “iteratively processing operands” in the Specification. The Specification does explain, however, that Conventional processors include one or more arithmetic logic units for performing iterative operations such as divide, square root and transcendental (e.g., SIN, COS) operations. Iterative arithmetic operations are conventionally executed until a result is produced that has a fixed, defined bit precision. That is, operands are iteratively processed to produce a result having full precision, i.e., a target precision such as the precision associated 3 As noted above, the “truncating” step of claim 5 also may include “masking,” as recited in claim 6. App. Br. 13. A relevant definition of “masking” is “[t]he process of using the mask operation to perform operations on bits . . .” and a relevant definition of the word mask is “[a] binary value used to selectively screen out or let through certain bits in data value.” MICROSOFT COMPUTER DICTIONARY 329 (5th ed. 2002). For example, certain bits in a data value may be made equal to zero in a resulting value. Appeal 2011-007940 Application 11/381,870 8 with a result register or a precision associated with the starting operands. Spec. ¶ 2. A relevant definition of the word “iterate” is “[t]o execute one or more statements or instructions repeatedly,”4 a relevant definition of the word “processing “ is “[t]he manipulation of data within a computer system,” and a relevant definition of the word “operand” is “[t]he object of a mathematical operation or a computer instruction.” MICROSOFT COMPUTER DICTIONARY 292, 378, 423 (5th ed. 2002) (emphasis added). Further, the “operands” of this “processing” step are described as being “of a first bit precision.” App. Br. 13. Thus, in view of the plain language of claim 1, these definitions indicating the ordinary meaning of the identified claim terms, and the disclosure of the Specification, we construe the “processing” step to mean processing operands having a first bit precision repeatedly, i.e., at least twice, to obtain a result having a second bit precision less than the first bit precision. This construction does not prohibit processing operands having other bit precisions, e.g., less than a first bit precision, but greater than a second bit precision, in the course of obtaining the result, but it requires that “operands of a first bit precision” are processed iteratively, i.e., repeatedly. Turning to the Appellant’s arguments concerning the significance of the recitation of claim 5, we note that other claims of an application can be valuable sources of enlightenment as to the meaning of a term of a challenged claim. See Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 4 Statements or instructions executed iteratively are said to be in a loop. MICROSOFT COMPUTER DICTIONARY at 292. Appeal 2011-007940 Application 11/381,870 9 1582 (Fed. Cir. 1996). Because claim terms generally are used consistently, the usage of a term, e.g., processing, in one claim may illuminate the meaning of the same term in other claims. See Rexnord Corp. v. Laitram Corp., 274 F.3d 1336, 1342 (Fed. Cir. 2001). Here, claim 5 depends directly from claim 1 and recites that the truncating of the operand occurs “before beginning the iterative processing.” App. Br. 13. As both the Examiner and Appellant agree, claim 5 incorporated each and every element of claim 1, and, therefore, claim 5 must include the “processing” step, meaning processing operands having a first bit precision repeatedly, i.e., at least twice, to obtain a result, as construed above. See App. Br. 8; Ans. 34. Nevertheless, Appellant argues that Dockser discloses repeatedly processing operands of a second bit precision, rather than a first bit precision. App. Br. 9; see Reply Br. 2–3 (numerical example). The Examiner again agrees stating that “the iterative execution is performed at the second bit precision, i.e. execution precision, wherein execution precision is equal to the truncated precision and less than the first bit precision, i.e. extended precision).” Ans. 35. We acknowledge the Examiner’s contentions concerning the interpretation of claim 1 in view of the recitations of claim 5. We are not persuaded, however, that Dockser discloses the “iterative processing” step of claim 1, as construed above, because, as the Examiner acknowledges, instead of obtaining a result with a bit precision less than the bit precision of the operand, as claim 1 requires, the iterative processing portion of Dockser’s process obtains a result having the same bit precision as the operand, the “execution precision.” See Ans. 30–31. In view of the construction of the “processing” step of claim 1, Appellant has persuaded us that Dockser fails to disclose the “processing” Appeal 2011-007940 Application 11/381,870 10 step of claim 1, and we reverse the anticipation rejection of that claim. Moreover, because each of independent claims 13, 23, and 36 contains an element corresponding to the missing element of claim 1, we also are persuaded of error in the Examiner’s rejection of those claims as anticipated by Dockser.5 See Ans. 39. Because each of dependent claims 5, 7, 11, 12, 16, 18, 22, 26, and 32–34 incorporates each and every element of its respective base claim, we also are persuaded of error in the Examiner’s rejection of those claims as anticipated by Dockser. Therefore, we do not sustain the anticipation rejection of claims 1, 5, 7, 11–13, 16, 18, 22, 23, 26, 32–34, and 36. 2. Claims 2–4, 6, 8–10, 14, 15, 17, 19–21, 24, 25, 27–31, and 35 The Examiner rejects claims 2–4, 6, 8–10, 14, 15, 17, 19–21, 24, 25, 27–31, and 35 as rendered obvious over Dockser in combination with other references. App. Br. 6. Nevertheless, the Examiner does not argue that any of those other references supply the deficiencies in the Dockser’s disclosure of the elements of the base claims of these rejected claims. Ans. 39–41. Because Appellant has persuaded us that the evidence of record does not support the rejection of the independent claims, we also do not sustain the obviousness rejections of these claims. CONCLUSION For the reason discussed, Appellant persuades us that the preponderance of the evidence does not support the Examiner’s rejection of 5 Claim 36 recites “means for iteratively processing operands of a first bit precision.” Appellant and the Examiner agree that structure corresponding to this means is disclosed in the Specification. App. Br. 5 (citing Spec. ¶ 18, Fig. 2); Ans. 9 (citing Spec. ¶ 15, Fig. 1.) Appeal 2011-007940 Application 11/381,870 11 claims 1, 5, 7, 11–13, 16, 18, 22, 23, 26, 32–34, and 36 under § 102(b) as anticipated by Dockser, or the rejection of claims 2–4, 6, 8–10, 14, 15, 17, 19–21, 25, 24, 27–31, and 35 under § 103(a) as unpatentable over Dockser in combination with Hirose, Pontius, or Arulpragasam. DECISION For the reasons set forth above, the Examiner’s decision rejecting claims 1–36 is reversed. REVERSED tj Notice of References Cited Application/Control No. 11/381,870 Applicant(s)/Patent Under Reexamination Appeal No. 2011-007940 Examiner Art Unit Page 1 of 1 U.S. PATENT DOCUMENTS * Document Number Country Code-Number-Kind Code Date MM-YYYY Name Classification A US- B US- C US- D US- E US- F US- G US- H US- I US- J US- K US- L US- M US- FOREIGN PATENT DOCUMENTS * Document Number Country Code-Number-Kind Code Date MM-YYYY Country Name Classification N O P Q R S T NON-PATENT DOCUMENTS * Include as applicable: Author, Title Date, Publisher, Edition or Volume, Pertinent Pages) U Microsoft Computer Dictionary (5th Ed. 2002) V W X *A copy of this reference is not being furnished with this Office action. (See MPEP § 707.05(a).) Dates in MM-YYYY format are publication dates. Classifications may be US or foreign. U.S. Patent and Trademark Office PTO-892 (Rev. 01-2001) Notice of References Cited Part of Paper No.