Ex Parte Dehner et al

Patent Trial and Appeal Board

Dec 28, 2018

14464134 (P.T.A.B. Dec. 28, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/464,134 08/20/2014
34814 7590 01/02/2019
NXP-LARSON NEWMAN, LLP
6501 William Cannon Drive West
Austin, TX 78735
FIRST NAMED INVENTOR
Leo G. Dehner
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
MT12579RC 2141
EXAMINER
VICARY, KEITH E
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
01/02/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte LEO G. DEHNER,
JAYAKRISHNAN C. MUNDARATH,
and PETER Z. RASHEV
Appeal2018-005290
Application 14/464,134 1
Technology Center 2100
Before JAMES R. HUGHES, ERIC S. FRAHM, and
MATTHEW J. McNEILL, Administrative Patent Judges.
McNEILL, Administrative Patent Judge.
DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-15 and 17-19. 2 We have jurisdiction under 35 U.S.C.
§ 6(b ).
We reverse.
1 According to the Appeal Brief, the real party in interest is NXP USA, Inc.
App. Br. 1.
2 There are no remaining rejections of claims 16 and 20, since the Examiner
has withdrawn the rejection under 35 U.S.C. § l 12(b). See Ans. 2.
Therefore, claims 16 and 20 are not before us on appeal.
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Application 14/464, 134
STATEMENT OF THE CASE
Introduction
Appellants' application relates to a single instruction multiple data
(SIMD) processor. Spec. ,r 13. A SIMD processor may be a vector
processor (VPU) having multiple arithmetic units (AUs) as subsidiary
processors. Id. Each AU includes a local memory and may simultaneously
implement commands. Spec. ,r 23. For example, the VPU may execute a
table transfer instruction that transfers one of a set of tables stored in a
lookup table memory to the local memory of each of the A Us in the VPU.
Spec. ,r 26. The VPU may then execute a table lookup instruction that
causes each AU to access its locally stored copy of the table to retrieve
lookup resultants. Spec. ,r 27.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A vector processor unit (VPU), the VPU
compnsmg:
a lookup table memory to store a set of lookup tables;
a plurality of arithmetic units (AUs), each AU comprising
local memory; and
instruction execution circuitry configured to, in response
to receiving a table transfer instruction,
execute the table transfer instruction, wherein the
table transfer instruction identifies a block of data
containing a first lookup table and wherein execution of
the table transfer instruction results in a transfer of the
block of data from the lookup table memory to the local
memory of each AU, and the instruction execution
circuitry further configured to, in response to receiving a
table lookup instruction, execute the table lookup
instruction which results in each AU accessing
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Application 14/464, 134
information stored at its corresponding local memory to
obtain a resultant value.
The Examiner's Rejections
Claims 1, 7, 8, 14, and 17 stand rejected under 35 U.S.C. § I03(a) as
being unpatentable over Redford (US 6,665,768; Dec. 16, 2003) and
Weybrew et al. (US 6,931,511 B 1; Aug. 16, 2005).
Claim 2 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over Redford, Weybrew, and Berg et al. (US 2003/0154349
Al; Aug. 14, 2003).
Claim 3 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over Redford, Weybrew, and Van Nostrand (US 5,008,752;
Apr. 16, 1991).
Claims 4, 5, 9-11, 13, 15, 18, and 19 stand rejected under 35 U.S.C.
§ I03(a) as being unpatentable over Redford, Weybrew, and Hongo et al.
(US 2004/0120420 Al; Jun. 24, 2004).
Claim 6 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over Redford, Weybrew, and Mimar (US 2013/0212353 Al;
Aug. 15, 2013).
Claim 12 stands rejected under 35 U.S.C. § I03(a) as being
unpatentable over Redford, Weybrew, Hongo, and Mimar.
ANALYSIS
In the Final Office Action, the Examiner finds the combination of
Redford and W eybrew discloses all the limitations of representative
independent claim 1, specifically:
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Redford discloses ... a plurality of arithmetic units (AUs)
(col. 3, line 25, processing elements 14 represent the multiple
data paths of the SIMD processor; col. 1, lines 25-26, complex
mathematical function), each AU comprising local memory ( col.
5, lines 52-53, one-to-one correspondence between data paths
and table copies; col. 1, lines 37-38, each processor to have an
individual small private memory for holding tables) ....
However, Redford does not explicitly disclose that the
instruction execution circuitry is further configured to, in
response to receiving a table transfer instruction, execute the
transfer instruction, wherein the table transfer instruction
identifies a block of data containing a first lookup table and
wherein execution of the table transfer instruction results in a
transfer of the block of data from the lookup table memory to the
local memory of each AU.
On the other hand, W eybrew explicitly discloses of
instruction execution circuitry further configured to, in response
to receiving a transfer instruction, execute the transfer
instruction, wherein the transfer instruction identifies a block of
data, and wherein execution of the transfer instruction results in
a transfer of the block of data from a source memory to a second
memory (col. 23, lines 53-56, the LSU 2816 also executes DMA
reading and writing instructions between the local memory 2 81 7
and the main memory, such as memory 1203 of FIG. 2, and
between the main memory and the lookup table within the VLUT
2811).
Final Act. 5---6. Appellants argue the Examiner's cited "Redford excerpt
cannot be a statement about loading the same table into multiple AUs. The
approach described for performing table lookups in Redford ... is for the
AUs to access central memory." App. Br. 9. Moreover, "Redford does not
even teach or suggest local memories for AUs." Reply Br. 2. Appellants
argue Weybrew does not cure the deficiencies of Redford. App. Br. 10. We
are persuaded by Appellants' arguments.
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Application 14/464, 134
Redford discloses a system 10 with a SIMD processor 12 having
multiple processing elements 14 and a memory 18. Redford, col. 3, 11. 20-
35; Fig. 1. Memory 18 is configured with multiple banks, referred to as
Banko through BankN, where multiple copies of a table that are used for
table lookups may be stored in multiple respective banks. See Redford, col.
3, 1. 42---col. 4, 1. 17. We agree with Appellants (see App. Br. 9; Reply Br. 2)
that Redford's processing elements 14 and banks of memory 18 do not meet
the claim 1 limitation of "a plurality of arithmetic units (AU s ), each AU
comprising local memory." As shown in Redford's Figure 1, memory 18 is
system memory, and is not part of processing elements 14. See Redford, col.
3, 11. 20-35; Fig. 1.
In the Answer, the Examiner clarifies that it is processing elements 14
in combination with Redford's private memories-which are described in
the "Background of the Invention" section as part of a "prior approach"
where "each processor [has] an individual small private memory for holding
tables" (Redford, col. 1, 11. 3 6-3 8}-that meets the claim 1 limitation "each
AU comprising local memory," and that suggests the limitation "wherein
execution of the table transfer instruction results in a transfer of the block of
data from the lookup table memory to the local memory of each AU," also
recited in claim 1. Ans. 6.
However, the Examiner has not provided a reason why one of
ordinary skill in the art would have used the private memories described as
part of a prior approach in Redford in processing elements 14 in Redford's
invention, which is especially important in light of Redford's disclosure that
"the use of these individual memories can be inefficient." Redford, col. 1, 11.
44--45. Further, the Examiner has not sufficiently explained why, in the
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proposed combination of Redford's processing elements 14 with Redford's
prior approach private memories, one would have transferred a block of data
containing a lookup table from a lookup table memory to each of the private
memories of the processing elements 14.
The Examiner asserts that "for a small private memory (i.e. a local
memory) of a processor (i.e. an AU) to hold a table (which is a block of
data), that table must necessarily have been previously transferred to the
small private memory." Ans. 5. This explanation, however, fails to address
the claim 1 feature of transferring a lookup table from a lookup table
memory "to the local memory of each AU." We note that Redford describes
the following: "[I]n accordance with the invention, multiple copies of a
table to be used for table look-ups can be stored in multiple respective banks
of the memory." Redford, col. 4, 11. 7-14. But Redford's disclosure of
storing copies of a lookup table in multiple banks of the system memory
does not suggest transferring a lookup table from a lookup table memory "to
the local memory of each AU" in the hypothetical combination of Redford's
processing elements 14 and prior approach private memories. In other
words, the Examiner has not shown that it would have been obvious in view
of Redford to both include private memories in processing elements 14, and
transfer a lookup table from a lookup table memory to the each of the private
memones.
The Examiner has not shown Weybrew cures the deficiencies of
Redford addressed above. The cited portion of W eybrew describes a
"load/store unit (LSU)" that "executes DMA reading and writing
instructions between the local memory 2817 and the main memory, such as
memory 1203 of FIG. 2, and between the main memory and the look-up
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table within the VLUT 2811." Final Act. 6; Weybrew, col. 23, 11. 43-56.
W eybrew teaches transferring data between memories, but does not suggest
transferring a lookup table from a lookup table memory to the local memory
of each AU, as required by claim 1.
We are, therefore, constrained by the record to find the Examiner
erred in rejecting independent claim 1, independent claims 9 and 14 which
recite commensurate limitations, and dependent claims 2-8, 10-13, 15, and
1 7-19 for the same reasons.
DECISION
We reverse the decision of the Examiner rejecting claims 1-15 and
17-19.
REVERSED
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