Ex Parte Corisis et al

Patent Trial and Appeal Board

Nov 15, 2016

12020899 (P.T.A.B. Nov. 15, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/020,899 01/28/2008
46844 7590 11/17/2016
PERKINS COIE LLP - Micron
PATENT-SEA
PO BOX 1247
SEATTLE, WA 98111-1247
FIRST NAMED INVENTOR
David J. Corisis
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
108298939US2 2869
EXAMINER
LEE, JAE
ART UNIT PAPER NUMBER
2899
NOTIFICATION DATE DELIVERY MODE
11/17/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
patentprocurement@perkinscoie.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DAVID J. CORISIS, LEE CROON KUAN,
and CHONG CHIN HUI
Appeal2015-003866
Application 12/020,899
Technology Center 2800
Before TERRY J. OWENS, CHRISTOPHER L. OGDEN, and
MICHAEL G. MCMANUS, Administrative Patent Judges.
OWENS, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
The Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
rejection of claims 1-5, 10, 12, 14, 16-19, 23, 61---63, and 71-73. We have
jurisdiction under 35 U.S.C. § 6(b).
The Invention
The Appellants' claimed invention is directed toward a carrierless
chip package for an integrated circuit device (Spec. 1:6-7). Claims 1 and 16
are illustrative:
Appeal2015-003866
Application 12/020,899
1. A device, comprising:
an integrated circuit chip including a backside surface
defining a backside plane;
a plurality of wire bonds conductively coupled to the
integrated circuit chip, the wire bonds individually having a
first end connected to the integrated circuit chip and a second
end at the backside plane, the second end defining a conductive
exposed portion that is an integrally formed part of the wire
bond, wherein the first end is opposite the second end;
an encapsulant material encasing at least portions of
(a) the integrated circuit chip and (b) the wire bonds, wherein
the backside surface of the integrated circuit chip at the
backside plane and the second ends of the wire bonds at the
backside plane are exposed through the encapsulant material,
and the encapsulant material has a mechanically altered bottom
surface at the backside plane extending between the second
ends of the wire bonds and the backside surface of the
integrated circuit chip;
a conductive structure including a plurality of bond pads
spaced from the second ends of the wire bonds; and
a plurality of conductive balls conductively coupling the
wire bonds to the conductive structure, the conductive balls
individually including a first side directly attached to a second
end of a wire bond at the backside plane and a second side
directly attached to a corresponding bond pad of the conductive
structure.
16. A device, comprising:
an integrated circuit chip including an exposed backside
surface defining a plane;
a plurality of wire bonds, the individual wire bonds being
operably coupled to the integrated circuit chip via a conductive
coupling, the individual wire bonds terminating at a distal end
with a mechanically altered conductive exposed portion that is
positioned in the plane defined by the backside surface, wherein
the conductive exposed portions are integrally formed parts of
the wire bonds;
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Appeal2015-003866
Application 12/020,899
an encapsulant material encasing the integrated circuit
chip except the backside surface and encasing the plurality of
wire bonds except the conductive exposed portions; and
a plurality of conductive balls directly conductively
coupling the conductive exposed portions to a conductive
structure.
Takabe
Tseng
Sato
Tellkamp
Siegel
Quinones
The References
US 6,258,632 Bl
US 6,395,580B1
US 2003/0008483 Al
US 6,518,647 Bl
US 6,700,190 B2
US 2005/0218300 Al
The Rejections
July 10, 2001
May 28, 2002
Jan. 9, 2003
Feb. 11,2003
Mar. 2, 2004
Oct. 6, 2005
The claims stand rejected under 35 U.S.C. § 103 as follows: claims 1,
2, 10, 12, 14, 65, 66, and 68, 69, 72, and 73 over Siegel in view of Takabe
and Sato, claims 16, 17, 23, 61, 63, 67, 70, and 71 over Siegel in view of
Takabe, Sato and Tseng, claims 3-5 and 18 over Siegel in view of Takabe,
Sato, Tseng and Quinones, claim 19 over Siegel in view of Takabe, Sato,
Tseng and Tellkamp and claim 62 over Siegel in view of Takabe, Sato,
Tseng and Saga. 1
OPINION
We reverse the rejections. We need address only the independent
claims ( 1, 16 and 65). 2 Claims 1 and 65 require an integrated circuit chip
1 The Examiner's statement of the rejections contains numerous errors, some
of which the Examiner tried to correct (Ans. 2-3). We have restated the
rejections such that they include the references applied to each claim.
2 The Examiner does not rely upon Quinones, Tellkamp or Saga for any
disclosure that remedies the deficiency in the references applied to the
independent claims (Ans. 15-17).
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Appeal2015-003866
Application 12/020,899
having a backside surface defining a backside plane, wire bonds having a
first end connected to the integrated circuit chip and a second end at the
backside plane, and a encapsulant material which encases at least a portion
of the integrated circuit and the wire bonds and has, at the backside plane, a
mechanically altered bottom surface extending between the wire bonds'
second ends and the integrated circuit chip's backside surface. Claim 16
requires an integrated circuit chip having a backside surface defining a
plane, and individual wire bonds terminating at an integrally-formed distal
end having a mechanically altered conductive exposed portion positioned in
the plane.
Siegel temporarily mounts an integrated circuit die (105) on a
carrier (110) and, after encasing a portion of the die (105) in a molding
compound, removes the carrier (110), thereby exposing the die (105)'s
backside surface and the molding compound's surface in the plane of that
backside surface (col. 4, 11. 41--42; col. 5, 11. 5-8; Fig. 4).
Takabe forms a semiconductor chip package by supporting a
semiconductor chip (1) on a plate (23), temporarily attaching to the
plate (23) distal ends of bonding wires (20) extending from the
semiconductor chip (1 ), encasing the semiconductor chip (1) and bonding
wires (20) in a molding compound, and removing the plate (23), thereby
exposing the semiconductor chip ( 1) 's backside surface and the distal ends
of the wiring bonds (20) (col. col. 4, 1. 67 - col. 5, 1. 18; col. 5, 11. 43-54;
Fig. 11 (b) ). "Because lead frames are not included within the molded resin
unit [8] and the wire bonds [20] are directly connected to connecting
electrodes [21; Fig. 1 l(c)], the molded resin unit can be made thinner and
the connecting electrodes arranged at high density" (col 4, 11. 11-15).
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Appeal2015-003866
Application 12/020,899
Sato discloses a semiconductor chip having opposing first and second
major surfaces with an alternating conductivity-type (p-n) layer
there between (i-f 18; Fig. 1 ). Sato polishes the semiconductor chip
mechanically or chemically from the side of the second major surface prior
to or after forming the alternating conductivity-type layer so that the
alternating conductivity-type layer has a predetermined thickness from the
first major surface (i-f 26).
Tseng uses chemical mechanical polishing to remove a layer (56) of
molding compound (50) below an integrated circuit (32) in a ball grid
array (30), thereby forming a new molding compound (50) surface (62) at
the integrated circuit chip (32)'s backside (60) plane and exposing, at that
plane, the distal ends of bonding wires (36) extending from the integrated
circuit chip (32) (col. 7, 11. 11-21; Figs. 4, 5).
The Examiner relies solely upon Sato to meet the Appellants' claim
requirement of a mechanically altered bottom surface of an encapsulant
material or a mechanically altered conductive exposed portion of wire
bonds' distal ends (Ans. 6, 9-10, 13). The Examiner asserts that "it would
have been obvious to a person having ordinary skill in the art at the time the
invention was made to incorporate a CMP [chemical mechanical polishing]
process to polish the surface of a semiconductor chip of Siegel and Takabe
since this will allow further reductions of thickness of the chip and achieve a
predetermined thickness defined by the user as taught by Sato" (id.) and that
Sato "teaches how CMP allows users to adjust a predetermined thickness to
be achieved (see Sato i-f26)" (Ans. 21 ).
Setting forth a prima facie case of obviousness requires establishing
that the applied prior art would have provided one of ordinary skill in the art
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Application 12/020,899
with an apparent reason to modify the prior art to arrive at the claimed
invention. See KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
The Examiner does not establish that Siegel's or Takabe's
semiconductor device includes an alternating conductivity-type layer such as
that of Sato or that Siegel's or Takabe' s semiconductor device is sufficiently
similar to that of Sato in some other way which would have provided one of
ordinary skill in the art with an apparent reason to reduce the thickness of
Siegel's or Takabe's semiconductor chip using the chemical or mechanical
polishing technique Sato uses to reduce the thickness of an alternating
conductivity-type layer. Nor does the Examiner establish that reducing the
thickness of Siegel's or Takabe' s semiconductor chip would result in the
mechanically altered bottom surface of the encapsulant material or the
mechanically altered conductive exposed portion of the wire bonds' distal
ends required by the Appellants' claims.
The Examiner asserts that Siegel discloses a carrier (110) lift off
procedure which produces the Appellants' mechanically altered surface
(Ans. 18-19).
Siegel does not disclose a carrier (110) lift-off procedure but, rather, is
silent as to how the carrier (110) is removed (col. 5, 11. 5-9). Regardless, the
Examiner provides no evidence which indicates that a lift-off procedure
produces a surface which is the same or substantially the same as the
Appellants' mechanically altered surface produced by methods such as
chemical mechanical polishing, grinding and etching (Spec. 20:4--10).
Thus, the Examiner has not established a prima facie case of
obviousness of the Appellants' claimed device.
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Appeal2015-003866
Application 12/020,899
DECISION/ORDER
The rejections under 35 U.S.C. § 103 of claims 1, 2, 10, 12, 14, 65,
66, and 68, 69, 72, and 73 over Siegel in view of Takabe and Sato,
claims 16, 17, 23, 61, 63, 67, 70, and 71 over Siegel in view of Takabe, Sato
and Tseng, claims 3-5 and 18 over Siegel in view of Takabe, Sato, Tseng
and Quinones, claim 19 over Siegel in view of Takabe, Sato, Tseng and
Tellkamp and claim 62 over Siegel in view of Takabe, Sato, Tseng and Saga
are reversed.
It is ordered that the Examiner's decision is reversed.
REVERSED
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