Ex Parte Conti

Patent Trial and Appeal Board

Apr 8, 2013

11557298 (P.T.A.B. Apr. 8, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte GREGORY R. CONTI
____________

Appeal 2010-008615
Application 11/557,298
Technology Center 2100
____________

Before JOHN A. JEFFERY, BARBARA A. BENOIT, and DAVID C.
McKONE, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s
rejection of claims 1-24. We have jurisdiction under 35 U.S.C. § 6(b). We
affirm-in-part.

STATEMENT OF THE CASE
Appellant’s invention restricts using a Direct Memory Access (DMA)
channel based on security rules. See generally Abstract. Claim 1 is
illustrative:
1. A system, comprising:

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a processor; a direct memory access (DMA) subsystem coupled to the
processor; and
a component coupled to the DMA subsystem via an interconnect
employing security rules, wherein, if the component requests a DMA
channel, the DMA subsystem restricts usage of the DMA channel based on
the security rules.

THE REJECTION
The Examiner rejected claims 1-24 under 35 U.S.C. § 102(b) as
anticipated by Moyer (US 2004/0243823 A1; published Dec. 2, 2004). Ans.
3-30.1

CONTENTIONS
The Examiner finds that Moyer discloses every recited element of
representative claim 1 including (1) a “processor” (e.g., master 12); (2) a
DMA subsystem (e.g., memory controller 32) coupled to the processor; and
(3) a “component” (e.g., one master or “various places” sending state
information) coupled to the DMA subsystem via an “interconnect” which is
said to correspond to (a) access protection control register 38; (b) conductors
62, 64 with state information 60; and/or (c) system interconnect 22. Ans. 3-
4, 31-33. According to the Examiner, this “interconnect” employs “security
rules” (e.g., access protection fields 72, 74, . . . , 80 and state information)
such that if the “component” requests a “DMA channel” (e.g., the DMA
operation path to access non-volatile memory 36 through the memory

1 Throughout this opinion, we refer to (1) the Appeal Brief filed September
15, 2009 (supplemented January 7, 2010) (“App. Br.”); (2) the Examiner’s
Answer mailed January 26, 2010 (“Ans.”); and (3) the Reply Brief filed
March 26, 2010 (“Reply Br.”).
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controller), the DMA subsystem restricts usage of the channel based on the
security rules. Ans. 3-4, 31-34.
Appellant argues that Moyer’s memory controller is not a DMA
subsystem, let alone a DMA subsystem coupled to a processor, since the
memory controller lacks DMA circuitry unlike masters 12 and 14. App. Br.
5; Reply Br. 3. Appellant adds that Moyer does not disclose a component
coupled to the DMA subsystem via an interconnect employing security
rules, nor does the DMA subsystem restrict usage of a DMA channel
requested by the component based on the security rules. App. Br. 5-6; Reply
Br. 4-5. Appellant also argues various limitations of other claims
summarized in the analysis below. The pivotal issue before us, then, is as
follows:

ISSUE
Under § 102, has the Examiner erred by finding that Moyer discloses
(1) a DMA subsystem coupled to a processor; and (2) a component coupled
to the subsystem via an interconnect employing security rules, where if the
component requests a DMA channel, the subsystem restricts usage of the
channel based on the security rules as recited in claim 1?

ANALYSIS
Claim 1
We begin by clarifying the Examiner’s mapping. As noted above, the
Examiner refers to Moyer’s masters 12, 14 in connection with both the
recited “processor” and “component.” See Ans. 3 (noting that masters 12
and 14 may be processors); see also id. (mapping the recited “component” to
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(1) one of reference numerals 12-20 in Moyer’s Figure 1; (2) a particular
master in Paragraph 0025; (3) “one of any number of masters as needed” in
Paragraph 0016; or (4) one of “various places” sending state information
which, according to Moyer’s Paragraph 0027, can be from masters 12 or 14).
In the Response to Arguments, the Examiner refers to (1) master 12 as a
“processor” (Ans. 31, 33), and (2) various masters in connection with the
recited “component” (Ans. 33).
Although the Examiner’s mapping is not a model of clarity in this
regard, we nonetheless understand the Examiner’s position to include a
scenario where (1) master 12 functions as the recited “processor,” and (2)
master 14 functions as the recited “component.” In this scenario, the
Examiner does not “double count” masters 12 and 14 as Appellant contends
(App. Br. 6), but rather maps different masters to distinct recited elements.
We see no error in this position, for Appellant does not identify any special
meaning of the terms “processor” and “component” in the Specification that
precludes mapping Moyer’s masters to these respective elements under the
Examiner’s interpretation. That Appellant’s Specification does not define
the terms “processor” and “component”—yet explicitly defines other
terms2—only bolsters the Examiner’s interpretation in this regard.
Nor do we find error in the Examiner’s mapping Moyer’s memory
controller 32 to the recited “DMA subsystem.” Even assuming, without
deciding, that the memory controller lacks DMA circuitry unlike the masters
as Appellant contends (Reply Br. 3), that does not preclude the Examiner’s

2 See, e.g., Spec ¶ 0013 (defining “including,” “comprising,” “couple,” and
“couples”); see also Spec ¶ 0015 (defining “hardware security
architecture”); Spec. ¶ 0019 (defining “interconnect qualifier” or
“qualifier”); Spec. ¶ 0029 (defining “in-band errors”).
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finding that the memory controller is a “DMA subsystem” at least to the
extent that its memory access capabilities are based on state information
involving DMA operations. See Ans. 3 (citing Moyer ¶¶ 0016, 0027), 31;
see also Moyer ¶ 0035 (noting that state information 60 can include a signal
from a DMA (e.g., masters 12 or 14) to indicate occurrence of a DMA
operation).
Moreover, as shown in Moyer’s Figure 1, both master 12
(“processor”) and master 14 (“component”) are coupled to memory
controller 32 (“DMA subsystem”) via system interconnect 22 and associated
conductors 48, 50, and 24. See Moyer ¶ 0013. Even assuming that Moyer’s
system interconnect functions as a bus as Appellant contends (App. Br. 5-6;
Reply Br. 4-5), the Examiner did not map the recited “interconnect” solely
to Moyer’s system interconnect 22, but rather also to access protection
control register 38 and conductors 62, 64 with state information 60. See
Ans. 3, 32-33 (mapping the recited “interconnect” to (1) access protection
control register 38; (2) conductors 62, 64 with state information 60; and/or
(3) system interconnect 22). Ans. 3-4, 31-33. Appellant fails to
persuasively rebut these findings, let alone the Examiner’s finding that
access protection control register 38 employs “security rules” such as the
access protection fields shown in Moyer’s Figure 2. Ans. 3, 32-33 (citing
Moyer ¶ 0021). Nor does Appellant persuasively rebut the Examiner’s
additional finding that by conveying state information (which also
constitutes “security rules” under the Examiner’s interpretation),
“interconnect” conductors 62 and 64 “employ” these rules. Ans. 32 (citing
Moyer ¶ 0027). In any event, Appellant’s contention that the Examiner’s
determination is based on “improper hindsight reconstruction” (App. Br. 6)
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is inapposite to the Examiner’s rejection which is based on anticipation—not
obviousness.
Lastly, despite Appellant’s contentions (App. Br. 6; Reply Br. 5), we
are unpersuaded of error in the Examiner’s finding that if the “component”
(master) requests a DMA “channel” (i.e., a DMA operation path to access
non-volatile memory 36 through the memory controller in Figure 1), the
“DMA subsystem” (memory controller) restricts usage of that channel based
on the security rules. Ans. 4, 34. Appellant’s contention that peripheral 18
or other slaves 20 do not request a DMA channel (Reply Br. 5) is inapposite
to the Examiner’s reliance on master 14 as corresponding to the requesting
component.
We are therefore not persuaded that the Examiner erred in rejecting
claim 1.

Claim 2
We also sustain the Examiner’s rejection of claim 2 reciting that the
security rules are associated with interconnect qualifiers selected from the
group consisting of the recited secure, debug, privilege, and instruction
qualifiers. As emphasized above and as the Examiner indicates (Ans. 36),
the claim merely requires that the interconnect qualifiers are selected from
the recited group which does not require selecting all qualifiers.
According to the Specification, an “interconnect qualifier” is “a signal
embedded in an access [that] reflects the state of the component that initiated
the access at the time the access was initiated.” Spec. ¶ 0019. Although
Appellant does not refer to this definition, Appellant nonetheless asserts that
Moyer does not disclose the recited qualifiers, and that Moyer’s masters do
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not have a privilege mode in addition to a secured and unsecured mode.
App. Br. 8-9; Reply Br. 11-14. These arguments not only fail to
persuasively rebut the Examiner’s findings regarding the recited privilege
qualifier, but also fail to show error in the Examiner’s other findings
regarding the other recited qualifiers. Ans. 4-6, 36-37.

Claim 3
We also sustain the Examiner’s rejection of claim 3 reciting that the
DMA subsystem selectively configures a DMA channel as a secure user
channel if the DMA channel request is one of a secure user mode access and
a secure privilege mode access. As emphasized above and as the Examiner
indicates (Ans. 37), the recited “one of” language does not require both
types of DMA channel requests: only one need be shown to meet the
limitation. Nevertheless, Appellant’s arguments (App. Br. 9-10; Reply Br.
14-15) do not persuasively rebut the Examiner’s particular findings from
Moyer as anticipating the recited limitations. Ans. 6 (citing Moyer ¶¶ 0016,
0022, 0025, 0035). In addition, Appellant’s contention that Moyer does not
teach a privilege mode in addition to a secure mode (App. Br. 9; Reply Br.
15) is not commensurate with claim 3 which does not require both user and
privilege mode access as noted above.

Claim 4
We also sustain the Examiner’s rejection of claim 4 reciting that the
DMA subsystem selectively configures a DMA channel as a public privilege
channel if the DMA channel request is one of (1) a public privilege mode
access, (2) a secure user mode access, and (3) a secure privilege mode
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access. As emphasized above and as the Examiner indicates (Ans. 38), the
recited “one of” language does not require the three recited types of DMA
channel requests: only one need be shown to meet the limitation.
Nevertheless, Appellant’s arguments (App. Br. 10; Reply Br. 15-17) do not
persuasively rebut the Examiner’s specific findings from Moyer as
anticipating the recited limitations, particularly the memory controller’s
ability to broaden access permissions for unsecured masters which
reasonably discloses configuring a “public privilege” channel if the channel
request is at least one of the recited requests. See Ans. 6 (citing Moyer ¶¶
0028-29, 0037, 0016, 0025). Accord Ans. 36 (referring to Moyer
broadening access to memory 36 in connection with a public channel).3 In
addition, Appellant’s contention that Moyer does not teach a privilege mode
in addition to a secure mode (App. Br. 10; Reply Br. 15) is not
commensurate with claim 4 which does not require the three recited mode
access types as noted above.

Claim 5
We also sustain the Examiner’s rejection of claim 5 reciting that the
DMA subsystem selectively configures a DMA channel as a public user
channel if the DMA channel request is one of (1) a public user mode access;
(2) a public privilege mode access; (3) a secure user mode access; and (4) a
secure privilege mode access. For reasons similar to those indicated for
claim 4, Appellant’s arguments (App. Br. 10-11; Reply Br. 17-19) do not

3 Although this finding is made in connection with claim 15, it nonetheless
informs our understanding of the Examiner’s position regarding public and
secure channels in Moyer and is therefore applicable here.
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persuasively rebut the Examiner’s findings based on Moyer. Ans. 7-8
(citing Moyer ¶¶ 0028-29, 0037, 0016, 0025). To the extent that Appellant’s
arguments are based on a distinction between the “public user channel”
recited in claim 5 and the “public privilege channel” recited in claim 4, we
are unpersuaded of error in the Examiner’s findings regarding these channels
given the scope and breadth of the associated limitations.

Claim 6
We also sustain the Examiner’s rejection of claim 6 reciting that the
DMA subsystem selectively configures a DMA channel as a secure privilege
channel if the DMA channel request is a secure privilege mode access.
Appellant’s arguments (App. Br. 11; Reply Br. 19-21) do not persuasively
rebut the Examiner’s findings based on Moyer. Ans. 8, 38-39 (citing Moyer
¶¶ 0028-29, 0037, 0016, 0025). Moreover, Appellant’s contention that
Moyer does not disclose more than one level of “secure channel” (App. Br.
11; Reply Br. 21) is unavailing and not commensurate with the scope of the
claim.

Claim 7
We also sustain the Examiner’s rejection of claim 7 reciting that the
DMA subsystem selectively configures a DMA channel as a debug channel
if the DMA channel request is one of (1) a debug mode access, and (2) a
functional mode access. As emphasized above and as the Examiner
indicates (Ans. 39), the recited “one of” language does not require both
recited types of DMA channel requests: only one need be shown to meet the
limitation. Nevertheless, Appellant’s arguments (App. Br. 11-12; Reply Br.
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21-22) do not persuasively rebut the Examiner’s findings based on Moyer.
Ans. 8, 39 (citing Moyer ¶ 0027). Although Moyer’s state information
relationship to debug operations is distinct from DMA operations as
Appellant contends (Reply Br. 22), nothing in the claim precludes Moyer’s
configuring the “channel” associated with a master according to the
Examiner’s mapping above for debugging operations—a master that can
have DMA functionality according to Moyer’s Paragraph 0035. In this
sense, then, the channel associated with the DMA master is a DMA channel
that would be configured for debugging if either recited request is made.
We are unpersuaded of error in the Examiner’s findings in this regard, for
Appellant’s arguments are not commensurate with the scope of the claim.4

Claim 8
We also sustain the Examiner’s rejection of claim 8 reciting that the
DMA channel is selectively used to transfer data to one of (1) a non-
executable memory space, and (2) an executable memory space based on an
instruction qualifier. As emphasized above and as the Examiner indicates
(Ans. 39), the recited “one of” language does not require both recited types
of memory spaces: only one need be shown to meet the limitation.
Nevertheless, Appellant’s arguments (App. Br. 12; Reply Br. 22-23) are not
commensurate with the scope of the claim and do not persuasively rebut the
Examiner’s findings based on Moyer. Ans. 8-9, 39 (citing Moyer ¶¶ 0027,
0019).

4 We note in passing that Appellant’s argument that Moyer fails to teach or
suggest configuring a DMA channel as a secure privilege channel (Reply Br.
22) is irrelevant here since it pertains to claim 6—not claim 7.
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Claim 9
We also sustain the Examiner’s rejection of claim 9 reciting that the
DMA channel can be used as an instruction channel selected from the group
of instruction channels consisting of (1) a public user instruction channel; (2)
public privilege instruction channel; and (3) secure user instruction channels.
As emphasized above and as the Examiner indicates (Ans. 39), the claim
merely requires that the instruction channel is selected from the recited
group which does not require selecting all channels. Nevertheless,
Appellant’s arguments (App. Br. 12; Reply Br. 23-26) are not commensurate
with the scope of the claim and do not persuasively rebut the Examiner’s
findings based on Moyer. Ans. 9-11, 39 (citing Moyer ¶¶ 0028-29, 0037,
0016, 0025).

Claim 10
We also sustain the Examiner’s rejection of claim 10 reciting that the
DMA subsystem asserts a security violation signal if at least one security
violation occurs, the security violation selected from the group consisting of
eight recited DMA channel configuration attempts. As emphasized above
and as the Examiner indicates (Ans. 39), the claim merely requires that the
security violation is selected from the recited group which does not require
selecting all violations. Nevertheless, Appellant’s arguments (App. Br. 13-
14; Reply Br. 26-31) are not commensurate with the scope of the claim and
do not persuasively rebut the Examiner’s findings based on Moyer. Ans. 11-
16, 39 (citing Moyer ¶¶ 0012, 0014, 0016, 0022, 0025, 0027-29, 0037).
Even assuming, without deciding, that Moyer lacks “complementary” access
permissions 58 to disclose a security violation signal as Appellant asserts
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(Reply Br. 30), Appellant still does not persuasively rebut the Examiner’s
alternative position relying on Moyer’s modified access permissions 66 as
disclosing the recited violation signal. See Ans. 11 (referring to
“complementary of ‘access permissions 58’ or ‘modified access permissions
66’” in connection with the recited security violation signal) (emphasis
added); see also id. (citing Moyer ¶ 0025 which notes that depending on
state information, access modification circuitry 40 may selectively modify
access permissions 58 to provide modified access permissions 66).

Claims 11-14
We do not, however, sustain the Examiner’s rejection of independent
claim 11 reciting, in pertinent part, (1) a configuration firewall configured to
receive DMA channel configuration requests, and (2) a violation handler
coupled to the firewall. The Examiner does not refer to a particular
structural element in Moyer as corresponding to the recited firewall, but
rather steps 84 through 88 of the flowchart in Figure 3. Ans. 16, 35 (finding
that “blocks 84, 86, and 88 are the configuration firewall”). Although these
steps are performed in connection with memory controller 32 (Moyer
¶ 0027), the Examiner has simply not articulated which elements of the
memory controller constitute the recited configuration firewall—a structural
element that is coupled to the violation handler according to claim 11. That
the Examiner maps Moyer’s access control circuitry 42 to the recited
violation handler, but does not map a corresponding structural element to the
recited firewall to which the handler is coupled only further undercuts the
Examiner’s anticipation rejection in this regard. That said, the Examiner
may have intended to map the elements of memory controller 32 that are
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upstream from access control circuitry 42 to the recited firewall. Or the
Examiner may be taking the position that the corresponding structure of
memory controller 32 that achieves the functions of steps 84 through 88 in
Figure 3 is inherently a configuration firewall that is coupled to the
identified “violation handler.” But we cannot say that this is necessarily the
case on this record; nor will we speculate in that regard here in the first
instance on appeal.
We therefore find that the weight of the evidence on this record favors
Appellant’s position, at least to the extent that the Examiner has failed to
show which structural elements in Moyer constitute the recited
“configuration firewall.” See App. Br. 6 (arguing that Moyer fails to teach a
configuration firewall). To the extent that this feature would have been
obvious, however, is a question not before us; nor will we speculate in that
regard here in the first instance on appeal. Accordingly, we are constrained
by this record to find that the Examiner erred in rejecting independent claim
11 and dependent claims 12-14 for similar reasons. Since this issue is
dispositive regarding our reversing the rejection of these claims, we need not
address Appellant’s other arguments pertaining to claims 12 and 14. App.
Br. 14-15; Reply Br. 32-33.

Claim 15
We do, however, sustain the Examiner’s rejection of claim 15 reciting
accessing a DMA subsystem, and if access is determined to be a secure
mode access, allowing a DMA channel to be configured as either one of a
secure channel and a public channel. We are unpersuaded of error in the
Examiner’s rejection for the reasons previously discussed and for the
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reasons indicated by the Examiner. Ans. 18-19, 35-36. We add that
Appellant’s arguments (App. Br. 8; Reply Br. 8-11) do not persuasively
rebut the Examiner’s reliance on Moyer’s broadening and restricting access
to memory 36 in connection with the recited public and secure channel
configurations.

Claim 16
We also sustain the Examiner’s rejection of claim 16 reciting that if
access is determined to be a debug mode access, then allowing a DMA
channel to be configured as a debug channel, but not a functional channel.
Appellant’s arguments (App. Br. 15-16; Reply Br. 33-34) are not
commensurate with the scope of the claim and do not persuasively rebut the
Examiner’s findings based on Moyer. Ans. 19, 39 (citing Moyer ¶ 0027).

Claim 17
We also sustain the Examiner’s rejection of claim 17 reciting that if
access is determined to be a functional mode access, then allowing a DMA
channel to be configured as either one of a debug channel and a functional
channel. Appellant’s arguments (App. Br. 16; Reply Br. 34) are not
commensurate with the scope of the claim and do not persuasively rebut the
Examiner’s findings based on Moyer. Ans. 19, 39 (citing Moyer ¶ 0027).

Claim 18
We also sustain the Examiner’s rejection of claim 18 reciting that if
access is determined to be a privilege mode access, then allowing a DMA
channel to be configured as either one of a privilege channel and a public
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channel. Appellant’s arguments (App. Br. 16-17; Reply Br. 35-36) are not
commensurate with the scope of the claim and do not persuasively rebut the
Examiner’s findings based on Moyer. Ans. 19-20, 39 (citing Moyer
¶¶ 0016, 0025, 0028-30, 0037).

Claim 19
We also sustain the Examiner’s rejection of claim 19 reciting that if
access is determined to be a secure user mode access, then allowing a DMA
channel to be configured as a public privilege channel. Appellant’s
arguments (App. Br. 17; Reply Br. 37-38) are not commensurate with the
scope of the claim and do not persuasively rebut the Examiner’s findings
based on Moyer. Ans. 20-21, 39 (citing Moyer ¶¶ 0012, 0014, 0016, 0027-
29, 0037).

Claim 20
We also sustain the Examiner’s rejection of claim 20 reciting that if
access is determined to be a secure privilege mode access, then allowing a
DMA channel to be configured as either one of a public user channel, a
public privilege channel, a secure user channel, and a secure privilege
channel. Appellant’s arguments (App. Br. 17-18; Reply Br. 38-40) are not
commensurate with the scope of the claim and do not persuasively rebut the
Examiner’s findings based on Moyer. Ans. 21-22, 39 (citing Moyer
¶¶ 0012, 0016, 0025, 0028-30, 0037).

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Claim 21
We also sustain the Examiner’s rejection of claim 21 reciting allowing
a DMA channel to be used as an instruction channel selected from the group
consisting of four recited DMA instruction channels. As emphasized above
and as the Examiner indicates (Ans. 39), the claim merely requires that the
instruction channel is selected from the recited group which does not require
selecting all such channels. Nevertheless, Appellant’s arguments (App. Br.
18-19; Reply Br. 40-42) are not commensurate with the scope of the claim
and do not persuasively rebut the Examiner’s findings based on Moyer.
Ans. 22-24, 39 (citing Moyer ¶¶ 0012, 0016, 0025, 0028-30, 0037).

Claim 22
We also sustain the Examiner’s rejection of claim 22 reciting that the
DMA subsystem asserts a security violation signal if at least one security
violation occurs, the security violation selected from the group consisting of
eight recited DMA channel configuration attempts. As emphasized above
and as the Examiner indicates (Ans. 39), the claim merely requires that the
security violation is selected from the recited group which does not require
selecting all violations. Nevertheless, Appellant’s arguments (App. Br. 19-
20; Reply Br. 42-47) are not commensurate with the scope of the claim and
do not persuasively rebut the Examiner’s findings based on Moyer. Ans. 24-
30, 39 (citing Moyer ¶¶ 0012, 0014, 0016, 0022, 0025, 0027-31, 0036-37).
Even assuming, without deciding, that Moyer lacks “complementary” access
permissions 58 to disclose a security violation signal as Appellant asserts
(Reply Br. 46), Appellant still does not persuasively rebut the Examiner’s
alternative position relying on Moyer’s modified access permissions 66 as
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disclosing the recited violation signal. See Ans. 24 (referring to
“complementary of ‘access permissions 58’ or ‘modified access permissions
66’” in connection with the recited security violation signal) (emphasis
added); see also id. (citing Moyer ¶ 0025 which notes that depending on
state information, access modification circuitry 40 may selectively modify
access permissions 58 to provide modified access permissions 66).

Claim 23
We do not, however, sustain the Examiner’s rejection of claim 23
reciting (1) locking a DMA channel’s use of qualifiers during a DMA
channel operation, and (2) unlocking a DMA channel’s use of qualifiers
after the operation is completed. Even assuming that Moyer’s Figure 3
shows receiving one DMA channel operation and receiving/using qualifiers
once at blocks 84 and 88 as the Examiner contends (Ans. 30), we cannot
say—nor has the Examiner shown—that this sequence necessarily (1) locks
the channel’s use qualifiers during a DMA channel operation, and (2)
unlocks that use after completing that operation. Accordingly, Appellant
(App. Br. 20-21) has persuaded us of error in the rejection of claim 23.

Claim 24
We do, however, sustain the Examiner’s rejection of claim 24 reciting
when a DMA channel is started, generating at least one qualifier that
corresponds to access rights of the DMA channel. Appellant’s arguments
(App. Br. 21; Reply Br. 48) are not commensurate with the scope of the
claim and do not persuasively rebut the Examiner’s findings based on the
sequence in Moyer’s Figure 3. Ans. 30, 39.
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CONCLUSION
Under § 102, the Examiner did not err in rejecting claims 1-10, 15-22,
and 24, but erred in rejecting claims 11-14 and 23.

ORDER
The Examiner’s decision rejecting claims 1-24 is affirmed-in-part.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART

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