Ex Parte Cogdill et al

Board of Patent Appeals and Interferences

Jun 27, 2012

10655964 (B.P.A.I. Jun. 27, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte MIKE COGDILL, IDIS RAMONA MARTINEZ, and LIDIA
MIHAELA WARNES
____________

Appeal 2010-005510
Application 10/655,9641
Technology Center 2800
____________

Before MARC S. HOFF, THOMAS S. HAHN, and
ELENI MANTIS MERCADER, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-22. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

1 The real party in interest is Hewlett-Packard Development Company, L.P.
Appeal 2010-005510
Application 10/655,964
2

STATEMENT OF THE CASE
Appellants’ invention concerns a circuit and system for a heavily
loaded memory module address bus. The circuit comprises a transmission
line having a dampening impedance between a driver and a branch point of
the transmission line. The circuit also has a termination impedance having
one end coupled to the transmission line between the dampening impedance
and the branch point (Spec. 3).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal.

A circuit for a memory module address bus comprising:

a transmission line comprising a dampening impedance between a
driver and a branch point of said transmission line; and

a parallel termination impedance having one end coupled to said
transmission line between said series dampening impedance and said branch
point, wherein said parallel termination impedance is on the same side of
any memory module as said driver;

said transmission line having branches from said branch point,
wherein ones of said branches are coupled to at least one memory module
interface.
REFERENCES

Buuck U.S. Pat. 5,583,449 Dec. 10, 1996
Mizukami U.S. Pat. 5,111,080 May 5, 1992
Johnson U.S. Pat. 6,715,014 B1 March 30, 2004

Appeal 2010-005510
Application 10/655,964
3
REJECTIONS
Claims 1-5, 7-19, and 21 stand rejected under 35 U.S.C. § 102(e) as
being anticipated by Johnson.
Claims 6 and 20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Johnson in view of Buuck.
Claim 22 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over Johnson in view of Mizukami.

ISSUES
Appellants argue that Johnson does not anticipate the invention
because Johnson’s termination impedance is not between the branch point
and the dampening impedance (App. Br. 9). Appellants further contend that
Johnson does not teach a parallel termination impedance “on the same side
of any memory module as said driver” (App. Br. 12). The Examiner finds
that the circuit of Figure 1 of Johnson is equivalent to Appellants’ claimed
invention (Ans. 10).
Appellants’ arguments and the Examiner’s findings present us with
the following issues:
1. Does Johnson teach a parallel termination impedance having one
end coupled to said transmission line between said series dampening
impedance and said branch point?
2. Does Johnson teach a parallel termination impedance on the same
side of any memory module as said driver?

Appeal 2010-005510
Application 10/655,964
4
PRINCIPLES OF LAW
“A rejection for anticipation under section 102 requires that each and
every limitation of the claimed invention be disclosed in a single prior art
reference.” See In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)
(quoting In re Paulsen, 30 F.3d 1475, 1478-79 (Fed. Cir. 1994)).

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellants’
arguments that the Examiner has erred. We disagree with Appellants’
conclusions. We concur with the findings and reasons set forth by the
Examiner in the action from which this appeal is taken and the reasons set
forth by the Examiner in the Examiner’s Answer in response to Appellants’
Appeal Brief. However, we highlight and address specific findings and
arguments regarding claim 1 for emphasis as follows.
We agree with the Examiner’s finding that Johnson teaches the
parallel termination impedance recited in the claims, connected according to
the claim language. Figure 2 of Appellants’ invention is reproduced below.

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Appeal 2010-005510
Application 10/655,964
8
memory modules 110 from driver 125; that is, current passes through
modules 110 before passing through impedance 130. Johnson teaches
termination impedance 326 on the same side of the memory modules as
driving source 312; current does not pass through memory modules on the
way to the termination impedance.
We agree with the Examiner that Johnson teaches all the limitations of
claims 1-5, 7-19, and 21. We will sustain the Examiner’s § 102 rejection.
Appellants’ arguments with regard to claims 6, 20, and 22, rejected
under § 103, amount to re-argument of the merits of claim 1. Thus, because
we find that Johnson teaches all the limitations of claim 1, we will also
sustain the § 103 rejection of claims 6, 20, and 22, for the same reasons.
CONCLUSIONS
1. Johnson teaches a parallel termination impedance having one end
coupled to said transmission line between said series dampening impedance
and said branch point.
2. Johnson teaches a parallel termination impedance on the same side
of any memory module as said driver.
DECISION
The Examiner’s decision rejecting claims 1-22 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R.§ 1.136(a)(1)(iv)(2010).

AFFIRMED

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