Ex Parte Capek et al

Board of Patent Appeals and Interferences

Feb 23, 2009

11065602 (B.P.A.I. Feb. 23, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte PETER G. CAPEK and ROBERT K. MONTOYE
____________

Appeal 2008-3842
Application 11/065,602
Technology Center 2100
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Decided:1 February 23, 2009
____________

Before JOHN C. MARTIN, HOWARD B. BLANKENSHIP, and
THU A. DANG, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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STATEMENT OF THE CASE
This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 1-5, which are all of the claims remaining in this
application. We have jurisdiction under 35 U.S.C. § 6(b).
We affirm the Examiner’s rejections against claims 1-5. We add a
new ground of rejection under 35 U.S.C. § 112, first paragraph against
claims 1-5.

Invention
Appellants’ invention relates to a computer usable storage apparatus
having a computer program product for enabling a processor to address
different registers within the processor. The computer program product
includes program code means (according to Appellants, described at Spec.
6:13-17) having an instruction (Spec. 8:26; Fig. 2 element 24) with a general
purpose register field (Fig. 2 elements rA and rB) and an apparent register
field (Fig. 2 element vD). The general purpose register field is capable of
directly indexing into a set of general purpose registers within the processor
(Spec. 8:28-29; Fig. 2 elements rA and rB directly index into general
purpose registers 25). The apparent register field is capable of indexing into
a set of apparent registers that indexes into a set of actual registers within the
processor (Spec. 8:16-24; Fig. 2 element vD indexes into apparent registers
21 that index into actual registers 22). The number of actual registers is
greater than the number of apparent registers (Fig. 2 apparent registers 21
are less than actual registers 22).

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Representative Claim
1. A computer usable storage apparatus having computer program
product for enabling a processor to address different registers within said
processor, said computer program product comprising:

program code means having an instruction with

a general purpose register field for directly indexing into
a set of general purpose registers within said processor;
and

an apparent register field for indexing into a set of
apparent registers that index into a set of actual registers
within said processor, wherein the number of said actual
registers is greater than the number of said apparent
registers such that any one of said actual registers is
capable of being designated by said instruction via at
least one of said apparent registers, and any one of said
actual registers is also capable of being directly
designated by said instruction.

Prior Art
The Examiner relies on the following references as evidence of
unpatentability.
Weaver 2003/0191924 A1 Oct. 9, 2003
Yamamoto 5,226,132 Jul. 6, 1993

Examiner’s Rejections
Claims 1-5 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Weaver and Yamamoto.

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Claim Groupings
Based on Appellants’ arguments in the Appeal Brief, we will decide
the appeal on the basis of claim 1 (see 37 C.F.R. § 41.37(c)(1)(vii)), which is
the sole independent claim on appeal.

ISSUES
(1) Have Appellants shown that the combination of Weaver and
Yamamoto does not teach or suggest actual registers located within a
processor that can be indirectly or directly designated by an instruction as
required by claim 1?
(2) Does the Specification as originally filed convey, with reasonable
clarity to those skilled in the art, possession of the invention including “any
one of said actual registers is capable of being designated by said instruction
via at least one of said apparent registers, and any one of said actual registers
is also capable of being directly designated by said instruction” as recited in
claim 1?

FINDINGS OF FACT
Specification; Claim 1
1. Claim 1 as originally filed recited that an actual register is
capable of being designated by an instruction via at least one apparent
register.
2. Claim 1 as originally filed also recited that an actual register is
capable of being directly designated by an instruction.
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3. Claim 1 as originally filed did not recite that the same
instruction is capable of both indirectly designating an actual register via an
apparent register and directly designating an actual register.
4. Claim 1 as amended indicates that an instruction is capable of
designating an actual register via an apparent register, and that the same
instruction is capable of directly designating an actual register (Amendment
filed December 19, 2006).
5. Appellants cited page 8, lines 25-29 as support for claim 1 as
amended (id.).
6. The Specification at page 8, lines 25-29 states that an
instruction can include an apparent register field for indexing into apparent
registers, and a standard register field for directly indexing into a set of
general purpose registers.
7. The Specification does not provide adequate written description
support for the claim 1 recitation of an instruction with a general purpose
register field, an apparent register field, and “any one of said actual registers
is capable of being designated by said instruction via at least one of said
apparent registers, and any one of said actual registers is also capable of
being directly designated by said instruction.”

Weaver
8. Weaver discloses an instruction having a field for direct index
into a register (¶¶ [0009], [0014], [0038], [0040]).
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9. Weaver discloses an apparent register field for indexing into a
set of apparent registers that index into a set of actual registers (Fig. 3A
element 90; ¶¶ [0040], [0042]).
10. The actual registers are within a processor (Weaver, Fig. 1; ¶¶
[0027], [0040]).
11. The number of actual registers is greater than the number of
apparent registers (id., Fig. 3A; ¶ [0040]).
12. Any one of the actual registers is capable of being indirectly
designated by an instruction via at least one of the apparent registers (id.,
Fig. 3A; ¶¶ [0036], [0042]).
13. Any one of the actual registers is capable of being directly
designated by an instruction (id., ¶¶ [0009], [0014], [0038], [0040], [0042]).
14. During instruction decode, apparent register numbers in an
instruction are mapped to the actual registers via an apparent register index
(id., ¶ [0042]).
15. The instruction, when in the cache, retains reference to the
apparent register (id.).
16. The same instruction, when in the processor’s execution
pipeline, refers to the actual register (id.).

PRINCIPLES OF LAW
Claim Interpretation
During examination, claims are to be given their broadest reasonable
interpretation consistent with the specification, and the language should be
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read in light of the specification as it would be interpreted by one of ordinary
skill in the art. In re American Academy of Science Tech Center, 367 F.3d
1359, 1369 (Fed. Cir. 2004) (citations omitted). The Office must apply the
broadest reasonable meaning to the claim language, taking into account any
definitions presented in the specification. Id. (citing In re Bass, 314 F.3d
575, 577 (Fed. Cir. 2002)).

Obviousness
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co., 383 U.S. 1, 17-
18 (1966).
The combination of familiar elements according to known methods is
likely to be obvious when it does no more than yield predictable results.
KSR Int’l Co. v. Teleflex, Inc., 127 S. Ct. 1727, 1739 (2007).

Written Description
To comply with the written description requirement of 35 U.S.C.
§ 112, first paragraph, an applicant must convey with reasonable clarity to
those skilled in the art that, as of the filing date sought, applicant was in
possession of the invention as now claimed. Vas-Cath, Inc. v. Mahurkar,
935 F.2d 1555, 1563-64 (Fed. Cir. 1991). One skilled in the art, reading the
original disclosure, must be able to immediately discern the limitations now
claimed. See Waldemar Link GmbH & Co. v. Osteonics Corp., 32 F.3d 556,
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558-59 (Fed. Cir. 1994). When an explicit limitation in a claim is not
present in the written description, it must be shown that a person of ordinary
skill would have understood, at the time the application was filed, that the
description requires that limitation. See Hyatt v. Boone, 146 F.3d 1348,
1353 (Fed. Cir. 1998).
One shows “possession” by descriptive means such as words,
structures, figures, diagrams, and formulas that fully set forth the claimed
invention. Lockwood v. American Airlines, Inc., 107 F.3d 1565, 1572 (Fed.
Cir. 1997). It is not sufficient for purposes of the written description
requirement that the disclosure, when combined with the knowledge in the
art, would lead one to speculate as to modifications that the inventor might
have envisioned, but failed to disclose. Id. A description which renders
obvious the invention for which the benefit of an earlier date is sought is not
sufficient. Id.

ANALYSIS
I. Section 103 rejection of claims 1-5
Appellants contend that neither Weaver nor Yamamoto teaches or
suggests the claimed actual registers that can be indirectly or directly
designated by the claimed instruction (App. Br. 6-7; Reply Br. 2).
Weaver discloses that an actual register is indirectly designated by an
instruction when the instruction is in the cache (FF 14-15), and the actual
register is directly designated by the instruction when the instruction is in the
processor’s execution pipeline (FF 16). Therefore, Weaver teaches and
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suggests the actual registers are indirectly and directly designated by the
instruction.
Furthermore, Weaver discloses that an instruction can directly
designate an actual register using a direct index field (FF 8, 13). Weaver
also discloses that an instruction can indirectly designate an actual register
using an apparent register index field (FF 9, 12). Directly designating an
actual register in an instruction using a direct index field as taught by
Weaver, and indirectly designating an actual register in the instruction using
an apparent register index field as taught by Weaver, appears to represent the
combination of familiar elements according to known methods. Appellants
have provided no evidence to the contrary.
We are not persuaded that providing both a direct index field and an
apparent register index field to allow an instruction to directly and indirectly
designate a register was “uniquely challenging or difficult for one of
ordinary skill in the art” (see Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485
F.3d 1157, 1162 (Fed. Cir. 2007) (citing KSR, 127 S. Ct. at 1741)).
Appellants contend that the combined teachings of Weaver and
Yamamoto do not teach or suggest the actual registers, as claimed, are
located within a processor (App. Br. 7). However, Weaver discloses that the
actual registers are located within a processor (FF 10). Therefore, the
combined teachings of Weaver and Yamamoto do in fact teach or suggest
the actual registers are located within a processor.
Appellants contend there is no motivation to combine the teachings of
Weaver and Yamamoto (App. Br. 5; Reply Br. 2). However, even assuming
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this to be true, Weaver alone teaches or suggests the elements of claim 1 as
discussed above.
Being not persuaded that claim 1 has been rejected in error, we sustain
the rejection of claims 1-5 under 35 U.S.C. § 103(a) as being unpatentable
over Weaver and Yamamoto.

II. New Ground of Rejection -- 37 C.F.R. § 41.50(b)
We reject claims 1-5 under 35 U.S.C. § 112, first paragraph, as failing
to comply with the written description requirement. The element “any one
of said actual registers is capable of being designated by said instruction via
at least one of said apparent registers, and any one of said actual registers is
also capable of being directly designated by said instruction” as recited in
claim 1 is not described in the Specification in such a way as to reasonably
convey to one skilled in the relevant art that the inventors, at the time the
application was filed, had possession of the claimed invention.
Claim 1 as originally filed recited that an actual register is capable of
being designated, via at least one apparent register, by an instruction (FF 1).
Claim 1 as originally filed also recited that an actual register is capable of
being directly designated by an instruction (FF 2). Claim 1 as originally
filed did not recite that the same instruction is capable of both indirectly
designating an actual register via an apparent register and also directly
designating an actual register (FF 3).
Claim 1 as amended recites that an instruction is capable of
designating an actual register via an apparent register, and that the same
instruction is capable of directly designating an actual register (FF 4).
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Appellants cited page 8 lines 25-29 as support for claim 1 as amended (FF
5). This portion of the Specification states that an instruction can include an
apparent register field for indexing into an apparent register, and a standard
register field for directly indexing into a set of general purpose registers (FF
6). The Specification here draws a distinction between indexing into general
purpose registers, which are directly designated by an instruction, and
indexing into actual registers, which are indirectly designated by the same
instruction via the apparent registers.
The Specification as originally filed does not convey to those skilled
in the art, through express, implicit, or inherent disclosure, possession of an
instruction having a general purpose register field, an apparent register field,
and “any one of said actual registers is capable of being designated by said
instruction via at least one of said apparent registers, and any one of said
actual registers is also capable of being directly designated by said
instruction” as recited in claim 1 as amended (FF 7).

CONCLUSIONS OF LAW
(1) Appellants have not shown that the combination of Weaver and
Yamamoto fails to teach or suggest actual registers located within a
processor that can be indirectly or directly designated by an instruction as
required by claim 1.
(2) Claims 1-5 in this application are not patentable under 35
U.S.C. § 112, first paragraph, because the Specification as originally filed
does not convey, with reasonable clarity to those skilled in the art,
possession of the invention including “any one of said actual registers is
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capable of being designated by said instruction via at least one of said
apparent registers, and any one of said actual registers is also capable of
being directly designated by said instruction” as recited in claim 1.

DECISION
The Examiner’s § 103(a) rejection of claims 1-5 is affirmed.
In a new ground of rejection, we have rejected claims 1-5 under
35 U.S.C. § 112, first paragraph, as failing to comply with the written
description requirement.
With respect to the affirmed rejection(s), 37 C.F.R. § 41.52(a)(1)
provides that “Appellant may file a single request for rehearing within two
months from the date of the original decision of the Board.”
In addition to affirming the Examiner’s rejection(s) of one or more
claims, this decision contains a new ground of rejection pursuant to
37 C.F.R. § 41.50(b). 37 C.F.R. § 41.50(b) provides that “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.”
37 C.F.R. § 41.50(b) also provides that Appellants, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of rejection to
avoid termination of the appeal as to the rejected claims:

(1) Reopen prosecution. Submit an appropriate amendment of
the claims so rejected or new evidence relating to the claims so
rejected, or both, and have the matter reconsidered by the
examiner, in which event the proceeding will be remanded to
the examiner. . . .
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(2) Request rehearing. Request that the proceeding be reheard
under § 41.52 by the Board upon the same record. . . .

Should Appellants elect to prosecute further before the Examiner
pursuant to 37 C.F.R. § 41.50(b)(1), in order to preserve the right to seek
review under 35 U.S.C. §§ 141 or 145 with respect to the affirmed rejection,
the effective date of the affirmance is deferred until conclusion of the
prosecution before the Examiner unless, as a mere incident to the limited
prosecution, the affirmed rejection is overcome.
If Appellants elect prosecution before the Examiner and this does not
result in allowance of the application, abandonment or a second appeal, this
case should be returned to the Board of Patent Appeals and Interferences for
final action on the affirmed rejection, including any timely request for
rehearing thereof.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED
37 C.F. R. § 41.50(b)

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