Ex Parte Bryant

Board of Patent Appeals and Interferences

Jan 14, 2004

08159461 (B.P.A.I. Jan. 14, 2004)

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The opinion in support of the decision being entered
today was not written for publication and is not binding
precedent of the Board.
Paper No. 43

UNITED STATES PATENT AND TRADEMARK OFFICE
_______________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
_______________

Ex parte FRANK R. BRYANT
______________

Appeal No. 2003-2130
Application 08/159,461
_______________

ON BRIEF
_______________

Before HAIRSTON, MCQUADE and WARREN, Administrative Patent Judges.

WARREN, Administrative Patent Judge.
Decision on Appeal and Opinion
We have carefully considered the record in this appeal under 35 U.S.C. § 134, including
the opposing views of the examiner, in the answer, and appellant, in the brief and reply brief, and
based on our review, find that we cannot sustain the grounds of rejection advanced on appeal:
appealed claims 1, 7 through 9, 34, 40 through 45, 56 and 58 through 65 under 35 U.S.C. § 112,
first paragraph, written description (answer, pages 4 and 6-8); and appealed claims 66 through
69 under 35 U.S.C. § 103(a) as being unpatentable over Geipel, Jr. et al. (Geipel) in view of
Haddad et al. (Haddad) (answer, pages 4-5 and 8).1

1 In addition to the appealed claims, claims 70 through 73 are also of record and have been
withdrawn from consideration by the examiner under 37 CFR § 1.142(b) in the Office action
mailed November 30, 2001 (Paper No. 33).
Appeal No. 2003-2130
Application 08/159,461
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It is well settled that the examiner has the burden of making out a prima facie case that
the appealed claims do not comply with § 112, first paragraph, written description requirement,
by setting forth evidence or reasons why, as a matter of fact, the written description in appellant’s
disclosure would not reasonably convey to persons skilled in this art that appellant was in
possession of the invention defined by the claims, including all of the limitations thereof, at the
time the application was filed. See generally, In re Alton, 76 F.3d 1168, 1172, 1175-76,
37 USPQ2d 1578, 1581, 1583-84 (Fed. Cir. 1996), citing In re Wertheim, 541 F.2d 257, 262-64,
191 USPQ 90, 96-97 (CCPA 1976). It is further well settled that while the written description
does not have to describe the invention later claimed in haec verba, such written description
“must . . . convey with reasonable clarity to those skilled in the art that . . . [appellant] was in
possession of the invention . . . now claimed.” Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555,
1563-64, 19 USPQ2d 1111, 1117 (Fed. Cir. 1991); see also Purdue Pharma L.P. v. Faulding
Inc., 230 F.3d 1320, 1323, 56 USPQ2d 1481, 1483 (Fed. Cir. 2000); Wertheim, 541 F.2d at
262-65, 191 USPQ at 96-98. Thus, where “the specification contains a description of the
claimed invention, albeit not in ipsis verbis (in the identical words), then the examiner or the
Board, in order to meet the burden of proof, must provide reasons why one of ordinary skill in
the art would not consider the description sufficient.” Alton 76 F.3d at 1175-76, 37 USPQ2d at
1583. A negative limitation which does not appear in the written description of the specification
as filed would cause the claim to violate the written description requirement of § 112, first
paragraph, if it introduces new concepts. See Ex parte Grasselli, 231 USPQ 393 (Bd. App.
1983), aff’d mem., 738 F.2d 453 (Fed. Cir 1984), citing In re Anderson, 471 F.2d 1237, 1
76 USPQ 331 (CCPA 1973).
The issue raised by the examiner involves the following italicized clause in the context of
illustrative claim 1 which is drawn to “[a] method for fabricating a portion of a semiconductor
device comprising” at least the steps wherein
the gate structure [is] formed by:
depositing the insulating oxide layer on the substrate;
depositing the polysilicon layer on the oxide layer;
implanting nitrogen ions only into the polysilicon layer; and
Appeal No. 2003-2130
Application 08/159,461
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annealing the layers to form a nitride layer only between the oxide layer and the
polysilicon layer . . . .
The examiner does not set forth the factual foundation for a prima facie case under this
section of the statute in the statement of the rejection (answer, page 4). However, it seems that
the examiner’s position is that the italicized phrase limiting the implanted nitrogen ions only to
the polysilicon layer constitutes a “negative limitation or exclusionary proviso” which is not
supported by a showing of fact in the specification and figures thereof in the same manner as the
specification and FIG. 2d of Haddad which “shows nearly the identical structure” to that in
present specification FIG. 10, that is, each of the figures depict implantation of nitrogen ions into
a structure wherein a polysilicon layer is on top of a silicon oxide layer (answer, pages 6-7).
Upon comparison of the respective disclosures, we find that the present specification
discloses in the written description that nitrogen ions are implanted into the polysilicon layer 22,
and upon annealing, silicon nitride layer 20 is formed in the polysilicon layer 22 at the boundary
or interface thereof with the silicon oxide layer 16, as shown in specification FIG. 4, with no
mention anywhere in the specification of any nitrogen implantation in silicon oxide layer 16
and/or subsequent formation of a silicon nitride layer in silicon oxide layer 16 during the
annealing step (e.g., page 9, line 4, to page 10, line 3, particularly, page 9, lines 20-28). In
contrast, we find that Haddad discloses that “as shown in FIG. 2d, a nitrogen ion implantation is
performed . . . [wherein] an implant energy . . . [implanted] nitrogen ions into the polysilicon
[layer] 14 and the [silicon] oxide [layer] 12” (col. 4, lines 7-12; italicized emphasis supplied).
Haddad further discloses in this respect that
FIG. 4 . . . [shows that] the nitrogen profile changes significantly such that there is a
pile-up of nitrogen at the polysilicon/silicon dioxide interface and again at the silicon
dioxide/substrate interface. In other words, within the silicon dioxide layer 12 there are
formed SixNy compounds at the interfaces of the silicon dioxide layer with adjacent
layers (see FIG. 4, peak points 18 and 20). [Col. 4, lines 32-41.]
Thus, according to the examiner, in the absence of express process conditions in the
present specification which confine nitrogen ion implantation and the formation of a silicon
nitride layer by subsequent annealing to the polysilicon layer boundary or interface with the
silicon oxide layer and evidence that this in fact occurs in similar manner to the evidence in
Haddad, there is no disclosure of such a result in the specification, and because the implantation
Appeal No. 2003-2130
Application 08/159,461
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and annealing step can therefore result in two silicon nitride layers as disclosed in Haddad,
appellant was not in possession of the method claimed using said clause in appealed claim 1 and
the other claims here rejected, at the time the application was filed (answer, pages 7-8).
Appellant contends that the passage of the specification we refer to above “only describes
implantation into the polysilicon layer without any teaching or suggestion of implantation [in]
other layers,” and submits that “[a]bsent some evidence that nitrogen implantation into the
polysilicon must inherently and necessarily result in implantation into other layers underlying the
polysilicon, the claim limitation is adequately described in the specification” (brief, pages 7-9;
see also reply brief, pages 2-5).
We agree with appellant. The limitation of the here rejected appealed claims to a method
wherein nitrogen ion implantation and annealing involves only the polysilicon layer is subject
matter specifically described in the written description of the specification and thus, simply does
not involve a negative limitation with respect to the remainder of the method as the examiner
contends. Indeed, as a matter of fact, the passage of the specification we refer to above makes
clear, as appellant argues, that the concept of implantation of nitrogen ions and subsequent
annealing involving only the polysilicon layer in the context of the disclosed method was within
his possession at the time the application was filed, which is all that is required by § 112, first
paragraph, written description requirement. To the extent that the examiner’s position can be
considered as under § 112, first paragraph, enablement requirement, the examiner has not
supplied the record with evidence that, prima facie, one of ordinary skill in this art would have
been unable to practice the method as claimed based on the information supplied in the written
description in the present specification.2 Indeed, the passage from Haddad we refer to above

2 It is well settled that under this statutory provision, the examiner has the burden of providing a
reasonable explanation, supported by the record as a whole, why the assertions as to the scope of
objective enablement set forth in the specification are in doubt, including reasons why the
description of the invention in the specification would not have enabled one of ordinary skill in
this art to practice the claimed invention without undue experimentation, in order to establish a
prima facie case under the enablement requirement of the first paragraph of § 112. See In re
Wright, 999 F.2d 1557, 1561, 27 USPQ2d 1510, 1513 (Fed. Cir. 1993); In re Wands, 858 F.2d
731, 737, 8 USPQ2d 1400, 1404 (Fed. Cir. 1988); In re Strahilevitz, 668 F.2d 1229, 1232,
212 USPQ 561, 563 (CCPA 1982); In re Marzocchi, 439 F.2d 220, 223-24, 169 USPQ 367,
369-70 (CCPA 1971). It is further well settled that “[a]n inventor need not . . . explain every
Appeal No. 2003-2130
Application 08/159,461
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clearly discloses to one of ordinary skill in this art that the implantation and annealing steps as
disclosed therein involved both the polysilicon and the silicon oxide layers.
Accordingly, on this record, we reverse the ground of rejection under 35 U.S.C. § 112,
first paragraph.
Turning now to the ground of rejection under 35 U.S.C. § 103(a), it is further well settled
that in order to establish a prima facie case of obviousness under § 103(a), the examiner must
show that some objective teaching, suggestion or motivation in the applied prior art taken as a
whole and/or knowledge generally available to one of ordinary skill in this art would have led
that person to the claimed invention as a whole, including each and every limitation of the claims
arranged as required by the claims, without recourse to the teachings in appellant’s disclosure.
See generally, In re Rouffet, 149 F.3d 1350, 1358, 47 USPQ2d 1453, 1458 (Fed. Cir. 1998);
Pro-Mold and Tool Co. v. Great Lakes Plastics, Inc., 75 F.3d 1568, 1573, 37 USPQ2d 1626,
1629-30 (Fed. Cir. 1996); In re Fritch, 972 F.2d 1260, 1265-66, 23 USPQ2d 1780, 1783-84
(Fed. Cir. 1992); In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed. Cir. 1992);
In re Laskowski, 871 F.2d 115, 10 USPQ2d 1397 (Fed. Cir. 1989); In re Fine, 837 F.2d 1071,
1074-76, 5 USPQ2d 1596, 1598-1600 (Fed. Cir. 1988). In these respects, it is well settled that a
reference stands for all of the specific teachings thereof as well as the inferences one of ordinary
skill in this art would have reasonably been expected to draw therefrom, see Fritch, 972 F.2d at
1264-65, 23 USPQ2d at 1782-83; In re Preda, 401 F.2d 825, 826, 159 USPQ 342, 344 (CCPA
1968), presuming skill on the part of this person. In re Sovish, 769 F.2d 738, 743, 226 USPQ
771, 774 (Fed. Cir. 1985).
The examiner relies on the combined teachings of Geipel and Haddad in rejecting
appealed independent claim 66, on which the other here rejected appealed claims depend. In
traverse, appellant’s arguments are based on the following limitations in context in illustrative

detail [of the invention] since he is speaking to those skilled in the art. What is conventional
knowledge will be read into the disclosure. Accordingly, an applicant’s duty to tell all that is
necessary to make or use varies greatly depending upon the art to which the invention pertains.”
In re Howarth, 654 F.2d 103, 105, 210 USPQ 689, 691 (CCPA 1981).
Appeal No. 2003-2130
Application 08/159,461
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claim 66: 3
patterning the polysilicon, nitride, and oxide layers to expose portions of the
substrate: and
reoxidizing the exposed substrate and polysilicon layer, forming oxide on exposed
surfaces of the patterned polysilicon layer and the exposed substrate,
wherein the oxide formed on the exposed substrate during reoxidation has a
thickness greater than the patterned oxide layer and includes a portion extending under
oxide formed on a peripheral surface of the patterned polysilicon layer during
reoxidation.
The disclosure of Geipel pertains to these limitations, with respect to which the examiner
contends that this reference shows
forming an oxide layer using thermal growth at a thickness of 150 to 800 angstroms on
a semiconductor substrate for a gate electrode (see col. 4 lines 36-38); depositing
phosphorous doped polysilicon on said gate insulator to a thickness of about 1000 to
5000 angstroms; patterning the oxide and the polysilicon to form a gate electrode and a
gate oxide (see col. 4-lines 42-57); and reoxidizing the exposed substrate and the
polysilicon layer to a thickness of 2500 angstroms, thereby forming oxide on exposed
surfaces of the patterned polysilicon layer and the exposed substrate (see col. 6-lines
22-26), and furthermore note that the oxide formed during the reoxidation step is
thicker than the previously patterned oxide layer, and since the structure of [Geipel]
and the instant application are the same inherently a portion of the oxide formed
during the reoxidation process extends under oxide formed on a peripheral surface of
the patterned polysilicon layer during reoxidation. [Answer, pages 4-5.]
Appellant argues that Geipel and Haddad do not show or suggest the second limitation
quoted above, and that “the reoxidation need NOT necessarily be thicker than the gate oxide”
(brief, page 11). The examiner responds that “the gate electrode oxide has a thickness of from
150 to 800 angstroms and the reoxidation oxide has a thickness of 2500 angstroms, which would
inherently lead to any undercut around an edge of the gate electrode (resulting from patterning)
be filled by the reoxidation oxide” (answer, page 8). In reply, appellant notes col. 6, lines 25-26
of Geipel, and argues that the reference “does not expressly state or depict formation of a
corresponding thickness of oxide either on the gate electrode sidewalls or over regions adjacent

3 We note here that a ground of rejection under § 103(a) based on this same combination of
references was affirmed by a prior panel of this Board in a decision entered February 28, 2001, in
the present application (Paper No. 27) in Appeal No. 1998-1439, which ground of rejection
involved different claims than now before us in the present appeal.
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Application 08/159,461
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the gate electrode” (reply brief, page 4).
In following the method steps disclosed in col. 4 of Geipel, we find that subsequent to the
deposition of phosphorous doped polysilicon over the 150 to 800 angstroms of silicon dioxide
which provides the gate insulating layer,
the last deposited layer of polysilicon is etched to form IGFET gate electrodes.
Retaining or removing and regrowing the gate dielectric over remaining portions of
the substrate to act as an ion implantation screen in the next step is optional at this
point.
Source and drain regions are next formed by ion implantation/drive in process using
both the polysilicon and [semi-recessed dielectric oxide] areas as a mask. [Col. 4, lines
35-60; emphasis supplied.]
In comparing the methods steps of Geipel with the limitations in claim 66 that we set
forth above, it is readily apparent that it is the step of “regrowing the gate electrode over the
remaining portions of the substrate” prior to the formation of source and drain regions in Geipel
which corresponds in certain respects to the claimed “reoxidizing” step. The deficiency in this
reference disclosure with respect to the claim limitations is two fold as appellant points out.
First, there is no teaching to “regrow” the gate oxide over all of the exposed surfaces of the
patterned substrate, which includes the polysilicon layer. And, second, there is no teaching of the
thickness of the “regrown” gate oxide on the exposed substrate. With respect to the latter, the
examiner’s inherency theory is untenable because it is based on further disclosure at col. 6, lines
22-26, which involves a step in a “preferred process related specifically to the source drain
junction formation” (col. 6, lines 8-9; see also col. 4, line 60, to col. 5, line 1, and col. 6, lines
11-21; and the Office action of November 30, 2001, Paper No. 33, page 3, last three lines of the
fourth full paragraph) and not the “regrowing” step.
Accordingly, on this record, we reverse the ground of rejection under 35 U.S.C. § 103(a).
The examiner’s decision is reversed.

Appeal No. 2003-2130
Application 08/159,461
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Reversed

KENNETH W. HAIRSTON )
Administrative Patent Judge )
)
)
)
JOHN P. MCQUADE ) BOARD OF PATENT
Administrative Patent Judge ) APPEALS AND
) INTERFERENCES
)
)
CHARLES F. WARREN )
Administrative Patent Judge )

Appeal No. 2003-2130
Application 08/159,461
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