10854990 (B.P.A.I. Feb. 16, 2012)

Ex Parte Blandy et al

Board of Patent Appeals and InterferencesFeb 16, 2012

10854990 (B.P.A.I. Feb. 16, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 10/854,990 05/27/2004 Geoffrey O. Blandy POU920040072US1 8612 46369 7590 02/16/2012 HESLIN ROTHENBERG FARLEY & MESITI P.C. 5 COLUMBIA CIRCLE ALBANY, NY 12203 EXAMINER PATEL, HETUL B ART UNIT PAPER NUMBER 2186 MAIL DATE DELIVERY MODE 02/16/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ Ex parte GEOFFREY O. BLANDY, JANET R. EASTON, LISA C. HELLER, WILLIAM A. HOLDER, DAMIAN L. OSISEK, GUSTAV E. SITTMANN, RICHARD P. TARCZA, and LESLIE W. WYMAN _____________ Appeal 2009-011281 Application 10/854,990 Technology Center 2100 ____________ Before MARC S. HOFF, ELENI MANTIS MERCADER, and BRADLEY W. BAUMEISTER, Administrative Patent Judges. MANTIS MERCADER, Administrative Patent Judge. DECISION ON APPEAL Appeal 2009-011281 Application 10/854,990 2 STATEMENT OF THE CASE Appellants appeal under 35 U.S.C. § 134(a) from the final rejection of claims 1 and 3-18. We have jurisdiction under 35 U.S.C. § 6(b). We reverse. INVENTION Appellants’ claimed invention is directed to input/output (I/O) operation requests from pageable storage guests interpreted without host intervention. For example, a capability is provided which allows a host, such as a z/VM® hypervisor software (108), and hardware/firmware of a processor, such as a zSeries processor (106), to interact with each other in a controlled cooperative manner in order to process V=V guest operating system Queued Direct I/O (QDIO) operations without requiring the transfer of control from/to the guest operating system (112) and the host (108). See Spec. ¶ [0044]; Fig. 1A. Claim 1, reproduced below, is representative of the subject matter on appeal. 1. A method of facilitating management of storage of a pageable mode virtual environment, said method comprising: managing storage of a pageable mode virtual environment, the managing being performed by a CPU of the pageable mode virtual environment absent intervention of a host of the pageable mode virtual environment, wherein the managing comprises resolving by the CPU a storage fault absent intervention by the host and eliminating context switching overhead between the host and a guest of the pageable mode virtual environment. Appeal 2009-011281 Application 10/854,990 3 THE REJECTIONS The Examiner relies upon the following as evidence of unpatentability: Kerr US 6,105,119 Aug. 15, 2000 Bugnion US 6,496,847 B1 Dec. 17, 2002 Yoder US 7,114,040 B2 Sep. 26, 2006 The following rejections are before us for review: 1. The Examiner rejected claim 1 under 35 U.S.C. § 103(a) as unpatentable over Bugnion in view of Kerr. 2. The Examiner rejected claims 3-18 under 35 U.S.C. § 103(a) as unpatentable over Bugnion in view of Kerr and Yoder. ISSUE The pivotal issue is whether the Examiner erred in finding that Bugnion in view of Kerr teaches the limitation of “managing being performed by a CPU . . . absent intervention of a host . . . eliminating context switching overhead between the host and a guest” as recited in claim 1. PRINCIPLE OF LAW “[T]he words of a claim ‘are generally given their ordinary and customary meaning.’” Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005). The claims, of course, do not stand alone. Rather, they are part of a “fully integrated written instrument” consisting principally of a specification that concludes with the claims. For that reason, claims “must be read in view of the specification, of which they are a part.” . . . [T]he specification “is always highly relevant to the claim construction analysis. Appeal 2009-011281 Application 10/854,990 4 Usually, it is dispositive; it is the single best guide to the meaning of a disputed term.” Phillips v. AWH Corp., 415 F.3d 1303, 1315 (Fed. Cir. 2005) (citations omitted). ANALYSIS Appellants argue that the Examiner’s reliance (Ans. 11-12) on the graphics processor of Kerr handling real-time multimedia, instead of the host CPU/MMX, to avoid host context switching, contradicts claim 1’s recitation of managing/resolving being performed by the CPU itself (App. Br. 7-8). Appellants also argue that the alternative interpretation proffered by the Examiner where Kerr’s CPU and graphics processor can be treated as a unit to read on the claimed CPU, goes against Kerr’s expressed teaching of purposefully physically separating the two processors (App. Br. 8), and thus one skilled in the art would not treat them as a unit (Reply Br. 3). We are persuaded by Appellants’ arguments. We agree with Appellants (App. Br. 7) that Kerr teaches using a graphics processor VSP instead of the CPU to avoid host context switching overhead (col. 30, ll. 10- 13). Thus, we agree with Appellants that Kerr teaches away from the teaching of managing by the CPU absent intervention of a host to eliminate context switching overhead. Furthermore, Claim 1 explicitly states that it is the CPU that manages rather than a host, thereby indicating that the host is software (i.e., not hardware like the CPU). When we turn to Appellants’ Specification this construction of the term “host” is validated by the reference to z/VM® hypervisor as a host which one skilled in the art would readily recognize as software. See Phillips, 415 F.3d at 1312, 1315. Thus, the Examiner’s Appeal 2009-011281 Application 10/854,990 5 reliance on a host CPU as taught by Kerr as meeting “a host” as recited in the claim is unreasonable and ignores the claim language which differentiates between a CPU and a host. Furthermore, the Examiner failed to construe the term “host” in light of the Specification and from the perspective of one skilled in the art. Id. We further agree with Appellants that the Examiner’s attempt to correct this flaw by treating both Kerr’s graphics processor VSP and the host CPU/MMX as a unit (Ans. 12) and as being equivalent to the claimed CPU contradicts Kerr’s expressed teaching of purposefully physically separating the two processors to avoid causing system imbalance (col. 26, ll. 49-54). For the aforesaid reasons we will reverse the Examiner’s rejection of independent claim 1 and for the same reasons the rejection of dependent claims 3-18. CONCLUSION The Examiner erred in finding that Bugnion in view of Kerr teaches the limitation of “managing being performed by a CPU . . . absent intervention of a host . . . eliminating context switching overhead between the host and a guest” as recited in claim 1. ORDER The Examiner’s rejection of claims 1 and 3-18 is reversed. REVERSED babc