Ex Parte Bjesse

Patent Trial and Appeal Board

Mar 30, 2016

12236646 (P.T.A.B. Mar. 30, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
12/236,646 09/24/2008 Per M. Bjesse
36454 7590 04/01/2016
SYNOPSYS, INC. C/O HA YNES BEFFEL & WOLFELD LLP
P.O. BOX366
HALF MOON BAY, CA 94019
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SYNP 1057-1 8320
EXAMINER
AISAKA, BRYCE M
ART UNIT PAPER NUMBER
2851
NOTIFICATION DATE DELIVERY MODE
04/01/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
docket@hmbay.com
pair_hbw@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte PER M. BJES SE
Appeal2014-007661
Application 12/236,646
Technology Center 2800
Before JEREMY J. CURCURI, JOSEPH P. LENTIVECH, and KARA L.
SZPONDOWSKI, Administrative Patent Judges.
CURCURI, Administrative Patent Judge.
DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's final
rejection of claims 1-5, 7-9, 11-20, 22-24, and 26-28. Final Act. 2-7. The
rejection of claims 6, 10, 21, and 25 has been withdrawn and the Examiner
indicated claims 6, 10, 21, and 25 are objected to and allowable if rewritten
in independent form to include the limitations of the base claim and any
intervening claims. Ans. 2. We have jurisdiction under 35 U.S.C. § 6(b).
Appeal2014-007661
Application 12/236,646
Claims 1-5, 7-9, 11-20, 22-24, and 26-28 are rejected under 35
U.S.C. § 103(a) as obvious over Jabir (US 2011/0010141 Al; Jan. 13, 2011)
and Bains (US 7,673,257 Bl; Mar. 2, 2010). Final Act. 2-7.
We reverse.
STATEMENT OF THE CASE
Appellant's invention relates to "integrated circuit design, and more
particularly to electronic design automation tools and tools for verification
and analysis of complex designs including memory." Spec. i-f 1. Claim 1 is
illustrative and reproduced below:
1. A method for processing a computer implemented
representation of a circuit design, comprising:
representing the circuit design in memory accessible by a computer as
a data structure defining a netlist as a plurality of nodes, and identifying a
first set of nodes that includes word-level datapath nodes for corresponding
words;
using the computer, segmenting word-level datapath nodes in the first
set of nodes in the data structure into segmented nodes having segment
widths corresponding to uniformly treated segments of the corresponding
words;
using the computer, finding reduced safe sizes for the segmented
nodes; and
using the computer, generating an updated data structure representing
the same circuit design, using the reduced safe sizes of the segmented nodes,
wherein the reduced safe sizes of at least some of the segmented nodes are
more than one bit.
ANALYSIS
The Examiner finds the combination of J abir and Bains teaches or
suggests all the limitations of claim 1. Final Act. 2-3. The Examiner finds
J abir teaches all limitations of claim 1, except for the recited "wherein the
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Application 12/236,646
reduced safe sizes of at least some of the segmented nodes are more than one
bit," for which the Examiner relies on Bains. Final Act. 3 (citing Bains col.
2, 11. 49-59; col. 4, 11. 5-35). The Examiner reasons:
It would have been obvious to one having ordinary skill in the art
at the time the invention was made that segmentation could be
carried out to result in nodes with sizes greater than one bit,
because doing so would allow the method to be carried out more
quickly or cheaply.
Final Act. 3.
Appellant presents, among other arguments, the following principal
arguments:
1.
[T]he Examiner is taking the position [(Final Act. 3 (citing Jabir
i-fi-182-85, 91, 95, 104))] that the initial and optimized netlists in
Jabir represent the same circuit design, simply because they
perform the same function. Applicant asserts that this is clearly
mistaken. The processes in J abir change the circuit design set
out by the initial netlist if they can, using the factorization and
optimization processes it describes. They do not create an
updated representation of the same, unchanged circuit design.
App. Br. 16-17.
11.
Bains et al. teaches the formation of a circuit design using word
level nodes. It does not teach reduction of word level nodes in
any sense. It is not clear how Bains et al. could be applied to
Jabir. Jabir already teaches the implementation of word level
nodes, and furthermore teaches that such word level node should
be decomposed into bit level nodes.
App. Br. 17-18.
111. The Examiner's rationale for combining the references is not
reasonable. See App. Br. 18-19.
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Appeal2014-007661
Application 12/236,646
Appellant persuades us that the Examiner erred in finding J abir
teaches the recited "generating an updated data structure representing the
same circuit design, using the reduced safe sizes of the segmented nodes";
that the Examiner erred in finding Bains teaches "wherein the reduced safe
sizes of at least some of the segmented nodes are more than one bit"; and
that the Examiner erred in concluding that the claimed invention would have
been obvious.
Regarding Appellant's argument i, we find this argument persuasive.
In the Examiner's Answer's Response to Argument, the Examiner explains
"The [E]xaminer notes that circuits can go through many different levels of
abstraction during compilation and implementation, and that a circuit which
has the exact same responses to a given set of inputs can be interpreted as a
'same circuit'." Ans. 4. However, we find this explanation unpersuasive,
and instead are persuaded by Appellant's explanation (Reply Br. 5): "Jabir
does not describe its initial and optimized netlists as representing the same
circuit. Rather, the optimization process in Jabir results in different circuits
that implement the same function."
Regarding Appellant's argument ii, we find this argument persuasive.
In the Examiner's Answer's Response to Argument, the Examiner explains
"Bains' disclosure teaches that decomposition into multi-bit chunks may be
beneficial because mapping at a higher (multi-bit) level can result in better
runtime/memory usage." Ans. 5. However, we find this explanation
unpersuasive, and instead are persuaded by Appellant's explanation (Reply
Br. 9): "Bains teaches that the operator may be decomposed into a number
of smaller operators. See, Bains, column 5, lines 30-46." That is, these
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Application 12/236,646
smaller operators in Bains are not reduced safe sizes for segmented nodes as
recited in claim 1.
Regarding Appellant's argument iii, we find this argument persuasive.
At least because of the errors in the Examiner's fact findings, the Examiner's
conclusion of obviousness lacks a rational underpinning.
We, therefore, do not sustain the Examiner's rejection of claim 1, or
of claims 2-5, 7-9, and 11-15, which depend from claim 1.
For the same reasons, we also do not sustain the Examiner's rejection
of claims 16 and 28, which recite "generate an updated data structure
representing the same circuit design, using the reduced safe sizes of the
segmented nodes, wherein the reduced safe sizes of at least some of the
segmented nodes are more than one bit," or the Examiner's rejection of
claims 17-20, 22-24, 26, and 27, which depend from claim 16.
ORDER
The Examiner's decision rejecting claims 1-5, 7-9, 11-20, 22-24,
and 26-28 is reversed.
REVERSED
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