Ex Parte Benisty et alDownload PDFPatent Trial and Appeal BoardMay 14, 201814075905 (P.T.A.B. May. 14, 2018) Copy Citation UNITED STA TES p A TENT AND TRADEMARK OFFICE APPLICATION NO. FILING DATE 14/075,905 67813 7590 BGL/ P.O. BOX 10395 CHICAGO, IL 60610 11/08/2013 05/14/2018 FIRST NAMED INVENTOR Shay Benisty UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www .uspto.gov ATTORNEY DOCKET NO. CONFIRMATION NO. 10519/2393 (MSA-1491-US) 1022 EXAMINER WONG,TITUS ART UNIT PAPER NUMBER 2184 MAIL DATE DELIVERY MODE 05/14/2018 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte SHAY BENISTY, TAL SHARIFIE, GIRISH DESAI, and ODED KARNI 1 Appeal2018-000184 Application 14/075,905 Technology Center 2100 Before BRUCE R. WINSOR, AARON W. MOORE, and DAVID J. CUTITTA II, Administrative Patent Judges. CUTITT A, Administrative Patent Judge. DECISION ON APPEAL Appellant appeals under 35 U.S.C. § 134(a) from the Examiner's Final Rejection of claims 1-20, all pending claims of the application. We have jurisdiction under 35 U.S.C. § 6(b ). We REVERSE. 1 Appellant is the Applicant, SanDisk Technologies LLC, which is the real party in interest according to the Brief. See Appeal Br. 3. Appeal2018-000184 Application 14/075,905 STATEMENT OF THE CASE Introduction Appellant's invention is directed to "[a] storage system ... that includes a buffer, a processor, a direct memory access (DMA) circuit, and a backend memory for data storage." Spec. ,r 3. The DMA circuit includes a "metadata generator [that] does not need to be implemented both in the DMA circuit and in firmware executed by the processor that executes other types of commands." Spec. ,r 12. 2 Exemplary Claim Claims 1, 8, and 15 are independent. Claim 1 is exemplary of the claimed subject matter and is reproduced below with limitation at issue emphasized: 1. A storage system comprising: a buff er configured to store host data when the host data is received from a host over a bus; a back end memory for data storage; a processor; a Direct Memory Access (DMA) circuit configured to copy data to the backend memory independently of the processor, the DMA circuit comprising: a data generator configured to generate the host data when the host data is not received from the host, wherein the DMA circuit is configured to copy the host data generated by the data generator to the backend memory independently of the 2 Throughout this Decision, we refer to: (1) Appellant's Specification filed November 8, 2013 ("Spec."); (2) the Final Office Action ("Final Act.") mailed April 20, 2016; (3) the Appeal Brief filed November 23, 2016 ("Appeal Br."); and ( 4) the Examiner's Answer ("Ans.") mailed February 23, 2017. 2 Appeal2018-000184 Application 14/075,905 processor when the host data is not received from the host, and to copy the host data in the buffer to the backend memory independently of the processor when the host data is received from the host; and a metadata generator configured to generate the metadata from the host data that is in the buffer when the host data is received from the host and to generate the metadata from the host data that is generated by the data generator when the host data is not received from the host. REFERENCE AND REJECTIONS Claims 1---6 and 8-20 stand rejected under 35 U.S.C. § I02(a)(l) as anticipated by Matsuda et al. (US 2008/0005386 Al; Jan. 3, 2008) ("Matsuda"). Final Act. 2---6. Claim 7 stands rejected under 35 U.S.C. § 103 as obvious over Matsuda. Our review in this appeal is limited only to the above rejections and the issues raised by Appellant. Arguments not made are waived. See 37 C.F.R. §§ 4I.37(c)(l)(iv), 4I.39(a)(l). ISSUE Based on Appellant's arguments, the dispositive issue presented on appeal is whether the Examiner errs in finding Matsuda discloses a "metadata generator configured to generate the metadata from the host data that is in the buffer when the host data is received from the host and to generate the metadata from the host data that is generated by the data generator when the host data is not received from the host," as recited in exemplary claim 1. 3 Appeal2018-000184 Application 14/075,905 ANALYSIS 35 U.S.C. § 102 Rejection Appellant argues Matsuda does not disclose a "metadata generator configured to generate the metadata from the host data that is in the buffer when the host data is received from the host and to generate the metadata from the host data that is generated by the data generator when the host data is not received from the host," as recited in independent claim 1. See Appeal Br. 7-12. Specifically, Appellant argues: the BCC generation circuit 22 and the FCC generation circuit 23 of Matsuda are not "configured to generate the metadata from the host data that is in the buffer when the host data is received from the host and to generate the metadata from the host data that is generated by" the dummy/padding generation circuit 25 "when the host data is not received from the host" (emphasis added). FIG. 1 of Matsuda clearly shows that the BCC generation circuit 22 and the FCC generation circuit 23 do not generate anything from the output the dummy/padding generation circuit 25. Appeal Br. 8 ( citing Matsuda Fig. 1 ). We are persuaded by Appellant's arguments. We agree with Appellant that the Examiner has not established Matsuda discloses a metadata generator that generates both metadata from the host data when the host data is not received from the host and metadata from the host data that is in the buffer when the host data is received from the host. To anticipate, a reference must disclose "within the four comers of the document not on1y an of the limitations clairned but also aH of the limitations arranged or combined in the same way as recited in the claim." Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008). 4 Appeal2018-000184 Application 14/075,905 Here, the Examiner has combined different disclosures not directly related to each other from Matsuda in formulating the anticipation rejection. See id. (For anticipation, "the [prior art] reference must clearly and unequivocally disclose the claimed [invention] or direct those skilled in the art to the [invention] without any need for picking, choosing, and combining various disclosures not directly related to each other by the teachings of the cited reference." (parenthetically quoting In re Arkley, 455 F.2d 586, 587 (CCPA 1972))). That is, even assuming the Examiner had established the "BCC generation circuit 22, FCC generation circuit 23 and dummy/padding generation circuit 25" of Matsuda's Figure 1 disclose the claimed metadata generator, the Examiner additionally relies on Matsuda's Figure 6 to disclose the buffer recited in the claimed metadata generator. See Final Act. 3, 11. 5- 6. Matsuda's Figure 1 is part of Appellant's Detailed Description of the Preferred Embodiments and, thus, describes Appellant's invention. See Matsuda ,r,r 49, 50. In contrast, Matsuda's Figure 6 is part of Appellant's Description of the Related Art and thus pertains to the related art rather than Appellant's invention. See Matsuda ,r,r 4, 14. The Examiner, therefore, relies on 'fvfatsuda's discussion of the related art to disclose the buffer recited in the metadata generator limitation, but relies on the embodiments pertaining to 1\1atsuda' s invention to disclose the remainder of the metadata generator limitation. Although "[ s]uch picking and choosing may be entirely proper in the rnaking of a 103, obviousness rejection ... it has no place in the rnaking of a l 02, anticipation rejection." ln re Arkley, 455 F.2d at 587-588. 5 Appeal2018-000184 Application 14/075,905 Because we agree with at least one of the dispositive arguments advanced by Appellant for claim 1, we need not reach the merits of Appellant's other arguments. Accordingly, based on the record before us, we do not sustain the Examiner's 35 U.S.C. § 102 rejection of independent claim 1, and independent claims 8 and 15 which recite commensurate limitations as those discussed above, and, for the same reasons, dependent claims 2---6, 8-14, and 16-20. 35 U.S.C. § 103 Rejection We also do not sustain the 35 U.S.C. § 103 rejection of claim 7, which depends from claim 1 and, thus, also recites the limitation at issue, for similar reasons. DECISION We reverse the Examiner's decision to reject claims 1---6 and 8-20 under 35 U.S.C. § 102(a)(l). We reverse the Examiner's decision to reject claim 7 under 35 U.S.C. § 103. REVERSED 6 Copy with citationCopy as parenthetical citation