Ex Parte Bedeschi et al

Patent Trial and Appeal Board

Feb 26, 2014

11906722 (P.T.A.B. Feb. 26, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/906,722 10/03/2007 Ferdinando Bedeschi ITO.0150US (P25699) 9124
21906 7590 02/26/2014
TROP, PRUNER & HU, P.C.
1616 S. VOSS ROAD, SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
HO, HOAI V
ART UNIT PAPER NUMBER
2827
MAIL DATE DELIVERY MODE
02/26/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte FERDINANDO BEDESCHI, CLAUDIO RESTA,
RICHARD FACKENTHAL, and RUILI ZHANG
____________

Appeal 2012-001277
Application 11/906,722
Technology Center 2800
____________

Before TERRY J. OWENS, PETER F. KRATZ, and JAMES C. HOUSEL,
Administrative Patent Judges.

KRATZ, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on an appeal under 35 U.S.C. § 134 from the
Examiner’s final rejection of claims 1, 3-11, and 13-30. We have
jurisdiction pursuant to 35 U.S.C. § 6.

Appeal 2012-001277
Application 11/906,722

2

Appellants’ claimed invention is directed to: (a) a method of
generating current in a periphery outside a memory core of a bit alterable
memory using an unboosted memory supply voltage, including driving the
current from the periphery into the core; (b) a memory device comprising a
core including bit alterable memory cells and a periphery outside the core
including a current generator for generating current for the cells using an
unboosted memory supply voltage, and mirror circuits for driving the current
from the periphery into the core; and (c) a system comprising a processor
and a lone-pair semiconductor memory including a core having specified
arrangement of lone-pair memory cells, a periphery including a current
generator for the cells, and mirror circuits to drive generated current into the
core using an unboosted memory supply voltage.
Claim 1 is illustrative and reproduced below:
1. A method comprising:
generating current in a periphery outside a memory core
of a bit alterable memory using an unboosted memory supply
voltage of the memory; and
driving the current from the periphery into the core.

The Examiner relies on the following prior art references as evidence
in rejecting the appealed claims:
Cho US 2005/0162303 A1 Jul. 28, 2005
Kang US 2006/0220071 A1 Oct. 5, 2006

The Examiner maintains the following grounds of rejection:
Appeal 2012-001277
Application 11/906,722

3
Claims 1, 3-11, and 13-30 stand rejected under 35 U.S.C. § 103(a) as
being anticipated by (obvious over) Kang in view of Cho.1
We reverse the stated rejection. Our reasoning follows.
It is well settled that the burden of establishing a prima facie case of non-
patentability resides with the Examiner. See In re Piasecki, 745 F.2d 1468,
1472 (Fed. Cir. 1984).
Here, the Examiner hinges the stated obviousness rejection as to
independent claims 1 and 11 on the Examiner’s assertion that the pulse
generation unit 540 of Kang is a current generator that generates a current
that is driven from the periphery into the core of a memory and couples that
assertion with the further assertions and argument that such a current
generator of Kang has the same functions as the current generator set forth in
Figure 6 of Cho and, as such, “it would have been obvious to a person of
ordinary skill in the art at the time of the invention was made to recognize
that these two current generators in Kang and Cho use the unboosted
memory supply voltage . . . .” (Ans. 4-6). Similarly, the Examiner relies on
the pulse generation unit 540 of Kang as a current generator in rejecting
independent claim 23 (Ans. 8).

1 In the Final Office action, the Examiner identifies the rejection as an
anticipation rejection under 35 U.S.C. § 102(e) notwithstanding that several
obviousness assertions were presented (FOA pp. 2-5). While the Examiner
continues to assert the phrase “anticipated by”, the rejection now maintained
in the Examiner’s Answer is a rejection under 35 U.S.C. § 103(a). While
Appellants identify the rejection as being under 35 U.S.C. § 102(e) as
presented by the Examiner in the Final Office action, Appellants’ arguments
address the combination of Kang and Cho as proposed by the Examiner in
the obviousness rejection set forth in the Answer (App. Br. 10-11).
Appeal 2012-001277
Application 11/906,722

4
As argued by Appellants, the pulse generation circuit 540 of Kang is a
pulse generator as Kang states it is rather than a current generator and it is
not employed for generating current using an unboosted memory supply
voltage that is driven from the periphery into the core of the memory, as
argued by the Examiner to be the case for the pulse generation circuit of
Kang taken alone, or with Cho (App. Br. 10-11; Reply Br. 1-2). The
description of the voltage boosting circuit 510, write driver 520, current
mirror 530, and pulse generation circuit 540 furnished by Kang supports
Appellants’ viewpoint (Kang, paras. 0030-0036; Fig. 5). Contrawise, the
Examiner’s references to certain claims, paragraphs, and figures of Kang do
not support the Examiner’s assertions (Ans. 4-10). Rather, Kang makes it
clear that the write current that is provided to memory cells is generated
from a boosted voltage and that the pulse generator generates certain sets of
pulses, which set pulses are employed via a current mirror 530 so as to
provide for a generated write current from the boosted voltage that is
controlled to correspond to a set current pulse waveform (paras. 0019, 0020,
0029-0036).
As argued by Appellants, the Examiner has not established that Cho
rectifies the Examiner’s apparent misapplication of Kang’s pulse generator
that produces pulses as being a current generator, particularly as applied
with respect to Appellants’ claimed subject matter (App. Br. 11).
In this regard, “rejections on obviousness grounds cannot be sustained
by mere conclusory statements; instead, there must be some articulated
reasoning with some rational underpinning to support the legal conclusion of
obviousness” being asserted. In re Kahn, 441 F.3d 977, 988 (Fed. Cir.
2006) (quoted with approval in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
Appeal 2012-001277
Application 11/906,722

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418 (2007)). After all, rejections based on § 103(a) must rest on a factual
basis with these facts being properly set forth and interpreted without
hindsight reconstruction of the invention from the prior art. See In re
Warner, 379 F.2d 1011, 1017 (CCPA 1967).
On this record, we reverse the Examiner’s obviousness rejection of
the appealed claims.

CONCLUSION
The Examiner’s decision to reject the appealed claims is reversed.

REVERSED

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