Ex Parte Bartling et al

Patent Trial and Appeal Board

Jun 15, 2017

13770041 (P.T.A.B. Jun. 15, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/770,041 02/19/2013 Steven Craig Bartling TI-72959 5000
23494 7590 06/19/2017
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS, TX 75265
EXAMINER
WANG, ZHIPENG
ART UNIT PAPER NUMBER
2115
NOTIFICATION DATE DELIVERY MODE
06/19/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte STEVEN CRAIG BARTLING and
SUDHANSHU KHANNA
Appeal 2017-004557
Application 13/770,0411
Technology Center 2100
Before JOHN A. JEFFERY, BRUCE R. WINSOR, and
JUSTIN BUSCH, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
Appellants seek our review under 35 U.S.C. § 134 of the Examiner’s
final decision rejecting claims 1—20. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.
1 According to Appellants, the real party in interest is Texas Instruments Inc.
Br. 1.
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Application 13/770,041
CLAIMED SUBJECT MATTER
Claims 1, 12, and 18 are independent claims. The claims generally
relate to a processing device executing a boot process. Spec. Abstract.
After a given amount of the boot process is completed, a plurality of non­
volatile logic element arrays store a boot state. Id. “When it is determined
that the processing device needs to restart from a boot state, energy can be
saved by restoring the machine state at that boot state instead of re-booting.”
Id. Claim 1 is representative and reproduced below:
1. A computing device apparatus providing non-volatile
logic based computing, the apparatus comprising:
a plurality of non-volatile logic element arrays;
a plurality of volatile storage elements;
at least one non-volatile logic controller configured to
control the plurality of non-volatile logic element arrays to store
a machine state represented by the plurality of volatile storage
elements and to read out a stored machine state from the plurality
of non-volatile logic element arrays to the plurality of volatile
storage elements;
wherein at least one of the plurality of non-volatile logic
element arrays is configured to store a boot state representing a
state of the computing device apparatus after a given amount of
a boot process is completed;
wherein the at least one non-volatile logic controller is
configured to control restoration of data representing the boot
state from the at least one of the plurality of non-volatile logic
element arrays to corresponding ones of the plurality of volatile
storage elements in response to detecting a reset event for the
computing device apparatus.
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Application 13/770,041
REJECTIONS
Claims 1 and 12 stand rejected under 35 U.S.C. § 102(a) as being
anticipated by Bower, III et al. (US 2012/0036346 Al; Feb. 9, 2012). Non-
Final Act. 2-4; Final Act. 2.2 3
Claims 2—11 and 13—20 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Bower and Shiga et al. (US 2006/0279977 Al;
Dec. 14, 2006). Non-Final Act. 4—11; Final Act. 2—3.
OPINION
Independent claim 1 recites, in part, controlling a plurality of non­
volatile logic element arrays to store a “machine state” represented by a
plurality of volatile storage elements. The Examiner finds that Bower
discloses moving “system states” from system memory to non-volatile
memory as hibernation files. Non-Final Act. 3^4 (citing Bower H 20—22).
The Examiner further finds the system states are described in paragraph 25
of Bower as “comprising contents of memory, registers, cache, the state of
peripheral devices, communication statuses with other computers.” Id.
Thus, the Examiner finds Bower discloses “storing machine state from
volatile memory to nonvolatile memory.” Id.
Appellants argue “[a] machine state is a state of combination logical
[sic] at a particular point in time. Bower teaches selectively reassembling
individual segment hibernation files into a hibernation file used to restore
system memory . . . ; not a machine state.” Br. 5 (citing Bower 121)
(emphases in original).
2 We note Bower also qualifies under 35 U.S.C. §§ 102(b) and (e).
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Application 13/770,041
We begin by construing the key disputed limitation of claim 1, which
recites, in pertinent part, “machine state.” Appellants’ Specification does
not define the term, and mentions machine state only in the context of
explaining that a machine state is represented by a plurality of volatile
storage elements that can be stored in, and read from, a plurality of non­
volatile logic element arrays. See e.g., Spec. 130. Although this description
informs our construction of the term “machine state,” it does not limit our
interpretation. Further, as is known in the art, a “state,” otherwise known as
a “status,” is a condition at a particular time of any of numerous elements of
computing (e.g., a device, bit, or other element) used to report on or to
control computer operations. Microsoft Computer Dictionary 497, 498
(5th ed. 2002). Therefore, under its broadest reasonable interpretation, a
“machine state” is a machine’s condition at a particular time used to report
on or to control computer operations.
Bower is directed to rebooting a computer system’s operating system
(OS). Bower Abstract. Bower explains that its “[sjystem memory is defined
as a lowest level of volatile memory in [the] computer.” Id. 114. Bower
discloses what it refers to as a hibernation process that involves copying
system states from its volatile system memory to hibernation files in non­
volatile storage, which can then be “used to re-install [or restore] the system
states.” Id. H 20, 21, 25. According to Bower, to reduce OS reboot time,
Bower takes checkpoint snapshots at pre-defmed checkpoints while the OS
is booting up. Bower 125. Although Bower discloses restoring memory
contents that may have been stored in a checkpoint snapshot, Bower
explicitly states that the checkpoint snapshots also include more than just
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Application 13/770,041
memory. Notably, “checkpoint snapshots are of system states that are
described in segments of system memory .... These system states describe
contents of memory, registers, cache, etc., as well as the state of peripheral
devices, input/output states, communication statuses with other computers,
etc.” Id. Bower stores its checkpoint snapshots in the aforementioned
hibernation files. Id. 126.
To the extent Appellants contend Bower’s hibernation files are used to
restore only system memory and not a machine state, we find such an
argument inconsistent with Bower’s disclosure in paragraphs 20 through 26,
as discussed above. Appellants are correct that Bower discloses that a
“hibernation file [is] used to restore system memory,” but Bower further
clarifies that the “hibernation file is used to re-install the system states in
system memory.” Bower 121. Thus, to the extent Bower discloses a
process of restoring memory, it includes memory containing the system
states. With the construction discussed above, we see no error in the
Examiner’s finding that Bower’s system state, describing contents of a
machine’s memory, registers, cache, input/output states, communication
statuses with other computers, etc. discloses a machine state under the
broadest reasonable interpretation.
For the reasons discussed above, we are unpersuaded of Examiner
error. Accordingly, we sustain the Examiner’s rejection of independent
claim 1. For similar reasons, we also sustain the Examiner’s rejection of
independent claim 18, which recites similar limitations. Further, we sustain
the Examiner’s rejection of claims 2—11, 19, and 20, which depend
therefrom and were not argued separately.
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Further, although Appellants argue independent claims 1 and 12
together (Br. 5), we note independent claim 12 does not recite a “machine
state.” Therefore, Appellants’ contention is not commensurate with the
scope of independent claim 12 and, thus, does not persuade us of error in the
Examiner’s rejection. See In re Self, 671 F.2d 1344, 1348 (CCPA 1982)
(limitations not appearing in the claims cannot be relied upon for
patentability). Accordingly, we sustain the Examiner’s rejection of
independent claim 12. Further, we sustain the Examiner’s rejection of
claims 13—17, which depend therefrom and were not argued separately.
DECISION
For the above reasons, we affirm the Examiner’s decision to reject
claims 1—20.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 41.50(f).
AFFIRMED
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