Ex Parte Ballantine et alDownload PDFBoard of Patent Appeals and InterferencesAug 26, 200910904565 (B.P.A.I. Aug. 26, 2009) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE _________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES __________ Ex parte ARNE W. BALLANTINE, KEVIN K. CHAN, JEFFREY D. GILBERT, KEVIN M. HOULIHAN, GLEN L. MILES, JAMES J. QUINLIVAN, SAMUEL C. RAMAC, MICHAEL B. RICE, and BETH A. WARD __________ Appeal 2009-002260 Application 10/904,565 Technology Center 2800 ___________ Decided: August 26, 2009 ___________ Before BRADLEY R. GARRIS, ADRIENE LEPIANE HANLON, and CHARLES F. WARREN, Administrative Patent Judges. HANLON, Administrative Patent Judge. DECISION ON APPEAL A. STATEMENT OF THE CASE This is an appeal under 35 U.S.C. § 134 from an Examiner’s decision rejecting claims 1-4 under 35 U.S.C. § 103(a) as unpatentable over the Appeal 2009-002260 Application 10/904,565 combination of Kim,1 Koga,2 and Chau.3 We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. The subject matter on appeal is directed to a crystalline polysilicon deposit in which the crystal grain size is controllably varied with the depth of the deposit. Spec., para. [0009]. Claim 1, reproduced below, is illustrative. 1. A CMOS transistor, comprising: a dielectric film; a gate conductor on the dielectric film, wherein the gate conductor includes a region of polycrystalline silicon, said region of polycrystalline silicon having a continuously varying grain size as a function of a distance measured from a surface of the dielectric film. App. Br. 9, Claims Appendix.4 B. ISSUE Have the Appellants shown reversible error in the Examiner’s conclusion that a gate conductor including a region of polycrystalline silicon having a “continuously varying grain size” as recited in claim 1 would have been obvious to one of ordinary skill in the art in view of the combined teachings of Kim and Koga?5 1 US 5,441,904 to Kim issued August 15, 1995. 2 US 6,690,030 B2 to Koga issued February 10, 2004. 3 US 5,710,450 to Chau issued January 20, 1998. 4 Appeal Brief dated October 24, 2006. 5 The Examiner did not rely on Chau to show that the claim limitation at issue would have been obvious to one of ordinary skill in the art. See Examiner’s Answer dated March 7, 2007 (“Ans.”) at 5 (“the Chau reference only rejects the limitation of forming a spacer which is only given in claim 4”). 2 Appeal 2009-002260 Application 10/904,565 C. FINDINGS OF FACT 1. Appellants’ Specification The Appellants’ Figure 3, reproduced below, illustrates an embodiment of the disclosed invention. Spec., para. [0018]. Appellant’s Figure 3 depicts a crystalline polysilicon deposit. According to this embodiment, polysilicon is deposited under conditions in which a selected parameter, e.g., pressure, is varied in a controlled manner so that as the depth of the deposit 302 increases, the crystal grain size continuously changes. Spec., para. [0028]. As illustrated in Figure 3, the polysilicon crystal grain size immediately adjacent to the dielectric layer 104 is the largest, and the crystal grain size diminishes continuously as the distance from the dielectric layer 104 increases. Spec., para. [0028]. 3 Appeal 2009-002260 Application 10/904,565 2. Kim Kim discloses a method for forming a gate electrode having two polysilicon layers, in which the grain size of one layer differs from the grain size of the other layer. Kim 1:10-19. The grain size of the first polysilicon layer can be either larger or smaller than the grain size of the second polysilicon layer. Kim 2:3-6. Kim discloses that no grain boundary within the first polysilicon layer aligns vertically with any grain boundary within the second polysilicon layer at the interface between the first and second polysilicon layers. Kim 2:21- 24. This misalignment prevents fluorine from diffusing or penetrating into the dielectric film. Kim 3:38-46, 52-55. 3. Koga Koga discloses that it is possible to continuously perform crystal growth processes of a polysilicon layer and a conductive layer. According to Koga, “[t]his makes it possible to reduce the number of process steps to manufacture the device.” Koga 9:66-10:4. D. ANALYSIS The Appellants argue that Kim discloses a gate electrode comprising two discrete layers of different grain sizes, not an area with a continuously varying grain size as recited in claim 1. App. Br. 5. The Examiner contends that Kim discloses a region of polycrystalline silicon having a varying grain size as a function of a distance measured from a surface of the dielectric film: wherein said varying grain size decreases continuously as a function of the distance measured from a surface of the dielectric film; and 4 Appeal 2009-002260 Application 10/904,565 wherein said varying grain size increases continuously as a function of the distance measured from a surface of the dielectric film (col. 2, ln. 44 – col. 3, ln. 30)[.] Ans. 3. The portion of Kim relied on by the Examiner relates to a method of forming a first polysilicon layer 3 having one grain size and a second polysilicon layer 4 having another grain size. The Examiner has failed to explain why this disclosure in Kim would have suggested a region of polycrystalline silicon having a “continuously varying grain size” as recited in claim 1. The Examiner also found that Koga discloses “continuously forming one layer from two layers in column 9, line(s) 65 – column 10, line 4.” The Examiner concluded that it would have been obvious to combine the teachings of Kim and Koga “because forming the one layer with different characteristics in one continuous process reduces the steps needed to form the layer.” Ans. 4. The Appellants argue that the portion of Koga relied on by the Examiner does not discuss forming a gate conductor layer with a continuously varying grain size. App. Br. 6. We agree. Koga discloses that it is possible to continuously perform crystal growth processes. See Koga 9:66-10:4. However, Koga does not disclose that grain size is continuously varied during such a process. Thus, it is unclear on this record why the teachings of Koga would have led one of ordinary skill in the art to continuously vary the grain size in either or both of the polysilicon layers disclosed in Kim. For the reasons set forth above, we cannot sustain the §103(a) rejection on appeal. 5 Appeal 2009-002260 Application 10/904,565 E. DECISION The decision of the Examiner is reversed. REVERSED tc CONNOLLY BOVE LODGE & HUTZ LLP (IBM MICROELECTRONICS DIVISION) P O BOX 2207 WILMINGTON, DE 19899-2207 6 Copy with citationCopy as parenthetical citation