Ex Parte Axford et al

Patent Trial and Appeal Board

Nov 15, 2012

11242131 (P.T.A.B. Nov. 15, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
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BEFORE THE PATENT TRIAL AND APPEAL BOARD
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Ex parte SIMON AXFORD, SIMON JOHN CRASKE, and
PAUL KIMELMAN
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Appeal 2010-003832
Application 11/242,131
Technology Center 2100
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Before ROBERT E. NAPPI, KALYAN K. DESHPANDE, and LARRY J.
HUME, Administrative Patent Judges.

DESHPANDE, Administrative Patent Judge.

DECISION ON APPEAL

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Application 11/242,131

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STATEMENT OF CASE1
The Appellants seek review under 35 U.S.C. § 134(a) of a final
rejection of claims 1-18, the only claims pending in the application on
appeal. We have jurisdiction over the appeal pursuant to 35 U.S.C. § 6(b).
We AFFIRM.

The Appellants invented memory protection mechanisms within data
processing systems where it is determined from the target address of a
memory access request, what attributes are associated with that target
address. Specification 1:5-8.
An understanding of the invention can be derived from a reading of
exemplary claim 1, which is reproduced below [bracketed matter and some
paragraphing added]:
1. Apparatus for processing data, said apparatus comprising:
[1] a source of memory access requests to respective
memory addresses within a memory address space;
[2] a programmable memory protection unit configured to
store programmable data defining a plurality of programmable
memory regions within said memory address space having
associated programmable memory attributes, said
programmable memory protection unit being operable to
receive a memory access request to a target memory address
from said source and, if said target address lies within one or
more of said plurality of programmable memory regions, then
to return an associated programmable memory attribute for said
target address; and

1 Our decision will make reference to the Appellants’ Appeal Brief (“App.
Br.,” filed May 18, 2009) and Reply Brief (“Reply Br.,” filed Nov. 2, 2009),
the Examiner’s Answer (“Ans.,” mailed Sep. 1, 2009), and Final Rejection
(“Final Rej.,” mailed Feb. 13, 2008).
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[3] a default memory protection unit hard-wired to define a
plurality of default memory regions within said memory
address space having associated default memory attributes, said
default memory protection unit being operable to receive said
memory request to said target memory address from said source
and, if said target address does not lie within one or more of
said plurality of programmable memory regions, then to return
an associated default memory attribute for said target address.

REFERENCES
The Examiner relies on the following prior art:
Cline
Kohn
Le
Segars
US 4,665,506
US 5,265,227
US 5,649,159
US 6,021,476
May 12, 1987
Nov. 23, 1993
Jul. 15, 1997
Feb. 1, 2000

REJECTIONS2
Claims 1-2, 4-6, 10-11, and 13-15 stand rejected under 35 U.S.C.
§103(a) as being unpatentable over Le and Segars.
Claims 3 and 12 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over Le, Segars, and Kohn.
Claims 8-9 and 17-18 stand rejected under 35 U.S.C. §103(a) as being
unpatentable over Le, Segars, and Cline.

ISSUES
The issue of whether the Examiner erred in rejecting claims 1-18 turns
on whether (1) the combination of Le and Segars fails to teach or suggest “a
default memory protection unit hard-wired to define a plurality of default

2 The previously submitted rejection of claims 7 and 16 under 35 U.S.C.
§ 112, first paragraph, has been withdrawn by the Examiner. Ans. 3.
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memory regions within said memory address space having associated default
memory attributes,” (2) the combination of Le and Segar fails to teach or
suggest a “programmable memory protect[ing] unit…then to return an
associated programmable memory attribute for said target address” or a
“default memory protection unit…, then to return an associated default
memory attribute for said target address,” (3) the Examiner failed to provide
an explicit analysis which establishes the reasons why one of ordinary skill
in the art would think to combine aspects of the prior art references, and (4)
Le and Segars teach away from the claimed invention.

ANALYSIS
Independent claims 1 and 10
The Appellants first contend that the combination of Le and Segars
fails to teach or suggest “a default memory protection unit hard-wired to
define a plurality of default memory regions within said memory address
space having associated default memory attributes,” as recited in
independent claim 1 and similarly recited in independent claim 10. App. Br.
11-13 and Reply Br. 3-4. The Appellants specifically argue that Le and
Segars fail to describe “a plurality of default memory regions.” App. Br. 11-
12. We disagree with the Appellants. Le describes a programmable sub-
block that may overlap with a main block, where “it is useful to have more
than one region.” Le 4:44-50. Segars further describes that it is possible
“memory regions defined do not completely fill the address space of the
memory, and hence there will be ‘holes’ in the address map.” Segars 2:49-
51. As correctly noted by the Examiner (Ans. 23-24), the broadest
reasonable interpretation term “regions” encompasses both the plurality of
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regions described by Le and the distinction between address spaces
described by Segars. As such, the Appellants’ argument is not found to be
persuasive.
The Appellants further contend that the combination of Le and Segars
fails to teach or suggest a “programmable memory protect[ing] unit…then to
return an associated programmable memory attribute for said target address”
or a “default memory protection unit…, then to return an associated default
memory attribute for said target address,” as recited in independent claim 1
and similarly recited in independent claim 10. App. Br. 13-15 and Reply Br.
6-7. We disagree with the Appellants. The Examiner has relied on Le to
describe memory units that return an associated memory attribute for the
target address. Ans. 4-7. The Examiner further relied on Segars to describe
a default memory protection unit that is hard-wired. Ans. 7. As such, the
Appellants’ argument is tantamount to an attack on the references
individually. Nonobviousness cannot be established by attacking the
references individually when the rejection is predicated upon a combination
of prior art disclosures. See In re Merck & Co. Inc., 800 F.2d 1091, 1097
(Fed. Cir. 1986).
Furthermore, the term “attribute” encompasses any characteristic of
the target address. The Specification describes an “attribute” to include
“read only, cacheable, noncacheable, not executable, etc.” Specification
2:15-17. As such, the “attributes” returned for a default or programmable
region are the same values as they relate to the target address, not whether
they are associated with the type of region (programmable or default). As
such, the Appellants’ argument that the combination of Le and Segars fails
to teach or suggest “default memory protection unit…, then to return an
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associated default memory attribute for said target address” is not
persuasive.
The Appellants additionally contend that “the Examiner fail[ed] to
provide an[] explicit ‘analysis’ which establishes the reasons why one of
ordinary skill in the art would think to combine aspects of the prior art
references.” App. Br. 15-17 and Reply Br. 7-8. We disagree with the
Appellants. The Examiner found that a person with ordinary skill in the art
would have been motivated to combine Le and Segars in order to increase
performance. Ans. 8. This motivation is further illustrated by Segars, which
describes that the use of hard-wired regions “can improve efficiency, since
there is no need for the address comparator logic to compare the address
with the address range.” Segars 3:2-8. As such, we find that the Examiner
has provided an articulated reasoning with some rational underpinning to
support the legal conclusion of obviousness.
The Appellants also contend that Le and Segars teach away from the
claimed invention. App. Br. 17-18 and Reply Br. 8-9. We disagree with the
Appellants. “A reference may be said to teach away when a person of
ordinary skill, upon reading the reference, would be discouraged from
following the path set out in the reference, or would be led in a direction
divergent from the path that was taken by the applicant.” Ricoh Co., Ltd. v.
Quanta Computer, Inc., 550 F.3d 1325, 1332 (Fed. Cir. 2008) (citations
omitted). A reference does not teach away if it merely expresses a general
preference for an alternative invention from amongst options available to the
ordinarily skilled artisan, and the reference does not discredit or discourage
investigation into the invention claimed. In re Fulton, 391 F.3d 1195, 1201
(Fed. Cir. 2004).
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Here, the Appellants merely allege that because Le and Segars only
describe a single region, Le and Segars teach away from the claimed
invention. App. Br. 17 and Reply Br. 8. The Appellants also merely allege
that Le and Segars teach away from transmitting attributes to any other
device. App. Br. 18 and Reply Br. 9. However, the Appellants fail to
provide persuasive evidence or rationale that Le or Segars discourage or
discredit the use of multiple regions or any evidence or rationale as to how
the disclosures of Le and Segars teach away from transmitting attributes to
other devices. Absent any rationale or evidence, we do not find the
Appellants’ argument persuasive.

Dependent claims 2-9 and 11-18
The Appellants contend that the Examiner erred in rejecting claims 2-
9 and 11-19 for the same reasons asserted in support of independent claims 1
and 10. App. Br. 18-21 and Reply Br. 9-11. We disagree with the
Appellants. The Appellants’ arguments in support of independent claims 1
and 10 were not found to be persuasive supra and are not persuasive here for
the same reasons.

CONCLUSION
The Examiner did not err in rejecting claims 1-18.

DECISION
To summarize, our decision is as follows.
 The rejection of claims 1-18 is sustained.
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2011).

AFFIRMED

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