Ex Parte Asher et al

Patent Trial and Appeal Board

Nov 19, 2013

11030010 (P.T.A.B. Nov. 19, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte DAVID H. ASHER, GREGG A. BOUCHARD,
RICHARD E. KESSLER, and ROBERT A. SANZONE
____________________

Appeal 2011-005636
Application 11/030,010
Technology Center 2100
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Before DEBRA K. STEPHENS, JOHN A. EVANS, and KERRY BEGLEY,
Administrative Patent Judges.

BEGLEY, Administrative Patent Judge.

DECISION ON APPEAL

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This is an appeal under 35 U.S.C. § 134(a) from the Examiner’s
decision finally rejecting claims 1, 3-9, and 11-17. We have jurisdiction
over the appeal under 35 U.S.C. § 6(b). We affirm.

STATEMENT OF CASE
The disclosed invention is directed to a network services processor
including an input/output bridge that avoids writing a cache block to
memory when the cache block is no longer required because the
corresponding portion of memory has been freed. (Abstract; Spec. 2:17-25.)
The input/output bridge avoids such memory updates by monitoring requests
to free portions of memory and upon detecting such a request, determining
whether the address of the relevant memory portion is stored in the cache.
(Abstract; Spec. 2:29-3:5.) If the address is stored in the cache, the
input/output bridge issues a command to clear the dirty bit associated with
the cache block, i.e., a bit marking whether the cache block has been
modified. (Abstract; Spec. 2:20-25, 3:3-7, 15:1-3.) Clearing the dirty bit
prevents the cache block from being written back to memory. (See Abstract;
Spec. 2:3-25.)
The present application includes claims 1, 3-9, and 11-17.1 Claims 1,
9, 16, and 17 are independent claims. Claim 1, reproduced below with the
disputed limitations in italics, is representative of the claimed subject matter:
1. A network services processor comprising:
a plurality of processors;
a coherent shared memory including a cache and a
memory, the coherent shared memory shared by the plurality of
processors; and

1 Claims 2 and 10 have been cancelled. (App. Br. 3; Final Office Action 2.)
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an input/output bridge coupled to the plurality of
processors and the cache, the input/output bridge monitoring
requests to free a selected portion in the memory and upon
detecting a request to free the selected memory portion,
comparing an address of the selected memory portion to
addresses stored in the cache and, in an event the address of
the selected memory portion is replicated in the cache, voiding
a memory update to the selected memory portion by issuing a
command to clear a dirty bit in a corresponding modified cache
block.

REJECTIONS AT ISSUE
Claims 1, 3, 7-9, and 13-17 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Vogt et al., U.S. Patent No. 6,622,214 B1 (issued
Sept. 16, 2003) (hereinafter “Vogt”) in view of Van Der Wolf et al., U.S.
Patent No. 6,226,715 B1 (issued May 1, 2001) (hereinafter “Van Der Wolf”)
and Zeller et al., U.S. Patent No. 5,623,633 (issued Apr. 22, 1997)
(hereinafter “Zeller”). (Ans. 4-13.)
Claims 4-6, 11, and 12 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Vogt in view of Van Der Wolf, Zeller, and Swenson
et al., U.S. Patent No. 4,415,970 (issued Nov. 15, 1983). (Id. at 13-18.)

ISSUE
Did the Examiner err in rejecting claims 1, 3-9, and 11-17 as obvious
under 35 U.S.C. § 103(a) because the combination of Vogt, Van Der Wolf,
and Zeller fails to teach or suggest “monitoring requests to free a selected
portion in the memory . . . , comparing an address of the selected memory
portion to addresses stored in the cache and, in an event the address of the
selected memory portion is replicated in the cache, voiding a memory update
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to the selected memory portion by issuing a command to clear a dirty bit in a
corresponding modified cache block,” as recited in independent claim 1 and
as similarly recited in independent claims 9, 16, and 17?

ANALYSIS
We have reviewed the Examiner’s rejections under 35 U.S.C. § 103(a)
in light of Appellants’ arguments in the Appeal Brief. We disagree with
Appellants’ assertion that the Examiner has erred. We adopt as our own
(1) the findings and reasons set forth by the Examiner in the Final Rejection
from which this appeal is taken and (2) the rebuttals to Appellants’
arguments expressed by the Examiner in the Examiner’s Answer. (See id. at
3-21; Final Office Action 2-18.) We highlight and address specific findings
and arguments below in addressing Appellants’ arguments on appeal.
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Appellants’ arguments on appeal focus on claim 1 and dispute
whether the cited references teach or suggest “monitoring requests to free a
selected portion in the memory” (“monitoring limitation”); “comparing an
address of the selected memory portion to addresses stored in the cache and,
in an event the address of the selected memory portion is replicated in the
cache” (“comparing limitation”); and “voiding a memory update to the
selected memory portion by issuing a command to clear a dirty bit in a
corresponding modified cache block” (“voiding limitation”), as recited in
claim 1. (See App. Br. 5-13.) With respect to these disputed limitations, the
Examiner finds that Vogt teaches the monitoring limitation; Zeller teaches
the comparing limitation and “voiding a memory update to the selected
memory portion” of the voiding limitation; and Van Der Wolf teaches the
voiding limitation. (Ans. 4-6; Final Office Action 3-5.)
The majority of Appellants’ assertions of error overlook the
Examiner’s grounds for rejecting claim 1 based on the combined teachings
of Vogt, Van Der Wolf, and Zeller, and the Examiner’s specific underlying
findings regarding which of these references teach which limitations of the
claim. Specifically, many of Appellants’ contentions dispute whether Vogt,
Van Der Wolf, and Zeller teach limitations or elements for which the
Examiner has not relied on the particular reference. (See App. Br. 7-8
(disputing whether Vogt teaches the voiding limitation); id. at 9-10
(disputing whether Van Der Wolf teaches the monitoring limitation and the
comparing limitation); id. at 10-12 (disputing whether Zeller teaches
“issuing a command to clear a dirty bit in a corresponding modified cache
block” of the voiding limitation).)
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Similarly, Appellants assert that the teachings of Vogt and Van Der
Wolf would not combine to disclose the invention recited in claim 1 because
a “hypothetical system” combining the two references “would not void a
memory update after comparing an address of the selected memory portion
to addresses stored in the cache and verifying that the address of the selected
memory portion is replicated in the cache.” (Id. at 12.) Yet Appellants’
argument does not reference Zeller, the third reference in the obviousness
rejection of claim 1—which the Examiner finds teaches the comparing
limitation that Appellants contend would be absent from a system combining
Vogt’s and Van Der Wolf’s teachings.
In sum, Appellants’ attacks on the references individually and for
allegedly failing to teach limitations the Examiner has not found the
references to disclose are misplaced and are not persuasive. See In re Merck
& Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986) (“Non-obviousness cannot be
established by attacking references individually where the rejection is based
upon the teachings of a combination of references.”); see also Banner Eng’g
Corp. v. Tri-Tronics Co., Nos. 93-1115, 93-1116, 93-1158, 1993 WL
432383, at *3 (Fed. Cir. Oct. 27, 1993) (holding that “[Appellant]’s attack
on the prior art—reference by reference—[wa]s not persuasive” because in
assessing obviousness, “references are read not in isolation but for what they
fairly teach in combination”).
We are similarly unpersuaded by Appellants’ arguments disputing
whether Vogt and Van Der Wolf teach limitations the Examiner finds these
references do teach. First, Appellants contend that Vogt does not disclose
the monitoring limitation, “monitoring requests to free a selected portion in
the memory,” as recited in claim 1, because Vogt “merely employs the in-
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use bit to determine if a particular address cell . . . is in use or free to receive
new bus transaction information and may use the in-use bit information to
direct its processor to initiate a bus transaction at a later date.” (App. Br. 8
(emphases added).) How the system disclosed in Vogt “employs” or
“use[s]” the in-use bit, however, is irrelevant to the Examiner’s finding that
Vogt teaches the monitoring limitation. The Examiner’s finding is based on
the existence of the in-use bit—not how the bit is used. (See Ans. 4, 18-19;
Final Office Action 3, 16-17.) Specifically, the Examiner finds that because
Vogt features an in-use bit set to indicate whether an address of memory is
free or in use, the system disclosed in Vogt must monitor requests to free
memory in order to appropriately set and clear the bit. (See Ans. 4, 18-19;
Final Office Action 3, 16-17; see also Vogt col. 26, ll. 31-37.) We concur
with the Examiner that this teaching in Vogt discloses the monitoring
limitation. Appellants’ arguments do not show any error in the Examiner’s
finding.
Second, Appellants contend that Van Der Wolf does not teach the
voiding limitation, “voiding a memory update to the selected memory
portion by issuing a command to clear a dirty bit in a corresponding
modified cache block,” as recited in claim 1. (App. Br. 9.) Specifically,
after discussing the teachings of Van Der Wolf regarding “prevent[ing]
write-back of data from the cache memory to the main memory” by
“clear[ing] a dirty bit for such data,” Appellants conclude that Van Der Wolf
“merely teaches preventing write-back of data from the cache memory to the
main memory dependent on the position of a particular address relative to a
current address of the address stream.” (Id.) Appellants, however, do not
explain why Van Der Wolf’s teachings allegedly do not disclose the voiding
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limitation. We find Appellants’ argument unpersuasive of error in the
Examiner’s finding that Van Der Wolf teaches the voiding limitation. The
Examiner has set forth with specificity a finding that Van Der Wolf, in
column 8, lines 19-43, teaches this limitation in its disclosure of “clear[ing]
the ‘dirty’ bit” for data in the cache, thereby preventing the data from being
“written back to main memory” and allowing the data to be overwritten.
(Van Der Wolf col. 8, ll. 19-43; Ans. 5; Final Office Action 6-7.) We agree
with the Examiner’s finding.
Finally, Appellants contend that one of ordinary skill in the art would
not look to combine the systems disclosed in Vogt, Van Der Wolf, and
Zeller to arrive at the system recited in claim 1. (App. Br. 12.) Further,
Appellants assert that such a combination “would require significant
alteration and would only be done in hindsight.” (Id. at 12-13.) The
Examiner has set forth findings and articulated reasoning with rational
underpinning to support the conclusion that claim 1 is obvious over the prior
art—specifically regarding the motivation to combine the cache-based
systems disclosed in Vogt, Van Der Wolf, and Zeller into the invention
recited in claim 1. (See Ans. 5-6; Final Office Action 4-5.) We concur with
the Examiner’s findings and reasoning. Appellants’ conclusory assertions
fail to provide sufficient evidence or argument to convince us that the
Examiner’s findings are erroneous, the Examiner’s reasoning is irrational, or
the Examiner improperly combined the references.
Accordingly, on this record, Appellants have not persuaded us of error
in the Examiner’s rejection of independent claim 1. Appellants’ arguments
for the patentability of all other pending claims, claims 3-9 and 11-17, rest
on Appellants’ assertions of error regarding the rejection of claim 1—which
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we have found to be without merit. (See App. Br. 13.) Thus, independent
claims 9, 16, and 17 fall with claim 1 and dependent claims 3-8 and 11-15,
in turn, fall with their respective base claim. We therefore sustain the
Examiner’s obviousness rejection of all pending claims.

DECISION
For the foregoing reasons, we affirm the Examiner’s rejection of
claims 1, 3-9, and 11-17 as unpatentable under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See
37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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